Lines Matching +full:- +full:- +full:-

31 #include "disas/dis-asm.h"
68 return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size); in extract_bits()
74 uint64 shift = 63 - msb; in sign_extend()
86 info->fprintf_func(info->stream, "Invalid register mapping index %" PRIu64 in renumber_registers()
88 siglongjmp(info->buf, 1); in renumber_registers()
93 * decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
95 * Map a 4-bit code to the 5-bit register space according to this pattern:
101 * | | | | | | | | | | | └---------------
102 * | | | | | | | | | | └---------------┐ |
103 * | | | | | | | | | └---------------┐ | |
104 * | | | | | | | | └---------------┐ | | |
112 * - ADDU[4X4]
113 * - LW[4X4]
114 * - MOVEP[REV]
115 * - MUL[4X4]
116 * - SW[4X4]
128 * decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type
130 * Map a 4-bit code to the 5-bit register space according to this pattern:
135 * | | | | | | | | | | | | └---------------------
136 * | | | | | | | | | | | └---------------┐ |
137 * | | | | | | | | | | └---------------┐ | |
138 * | | | | | | | | | └---------------┐ | | |
139 * | | | | | | | | └---------------┐ | | | |
150 * - MOVE.BALC
151 * - MOVEP
152 * - SW[4X4]
164 * decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type
166 * Map a 3-bit code to the 5-bit register space according to this pattern:
171 * | | | └-----------------------
172 * | | └-----------------------┐ |
173 * | └-----------------------┐ | |
174 * └-----------------------┐ | | |
176 * ┌-------┘ | | | | | | |
177 * | ┌-------┘ | | | | | |
178 * | | ┌-------┘ | | | | |
179 * | | | ┌-------┘ | | | |
186 * - ADDIU[R1.SP]
187 * - ADDIU[R2]
188 * - ADDU[16]
189 * - AND[16]
190 * - ANDI[16]
191 * - BEQC[16]
192 * - BEQZC[16]
193 * - BNEC[16]
194 * - BNEZC[16]
195 * - LB[16]
196 * - LBU[16]
197 * - LH[16]
198 * - LHU[16]
199 * - LI[16]
200 * - LW[16]
201 * - LW[GP16]
202 * - LWXS[16]
203 * - NOT[16]
204 * - OR[16]
205 * - SB[16]
206 * - SH[16]
207 * - SLL[16]
208 * - SRL[16]
209 * - SUBU[16]
210 * - SW[16]
211 * - XOR[16]
222 * decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding
225 * Map a 3-bit code to the 5-bit register space according to this pattern:
229 * | | | | | | | └-----------------------
230 * | | | └-----------------------┐ |
231 * | | └-----------------------┐ | |
232 * | └-----------------------┐ | | |
233 * └-----------------------┐ | | | |
235 * ┌-------┘ | | | | | | |
236 * | ┌-------┘ | | | | | |
237 * | | ┌-------┘ | | | | |
248 * - SB[16]
249 * - SH[16]
250 * - SW[16]
251 * - SW[GP16]
262 * decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type
264 * Map a 2-bit code to the 5-bit register space according to this pattern:
269 * | | | └-------------------
270 * | | └-------------------┐ |
271 * | └-------------------┐ | |
272 * └-------------------┐ | | |
280 * - MOVEP
281 * - MOVEP[REV]
292 * decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type
294 * Map a 2-bit code to the 5-bit register space according to this pattern:
299 * | | | └-----------------
300 * | | └-----------------┐ |
301 * | └-----------------┐ | |
302 * └-----------------┐ | | |
310 * - MOVEP
311 * - MOVEP[REV]
322 * decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type
324 * Map a 1-bit code to the 5-bit register space according to this pattern:
329 * | └---------------------
330 * └---------------------┐ |
340 * - MOVE.BALC
352 return 0ll - d; in neg_copy()
374 return d == 127 ? -1 : (int64)d; in encode_eu_from_s_li16()
418 info->fprintf_func(info->stream, "Invalid GPR register index %" PRIu64, in GPR()
420 siglongjmp(info->buf, 1); in GPR()
432 bool use_gp = gp && (counter == count - 1); in save_restore_list()
456 info->fprintf_func(info->stream, "Invalid FPR register index %" PRIu64, in FPR()
458 siglongjmp(info->buf, 1); in FPR()
472 info->fprintf_func(info->stream, "Invalid AC register index %" PRIu64, in AC()
474 siglongjmp(info->buf, 1); in AC()
481 img_address address = info->m_pc + value + instruction_size; in ADDRESS()
1421 * ABS.D fd, fs - Floating Point Absolute Value
1426 * fmt -----
1427 * fs -----
1428 * fd -----
1443 * ABS.S fd, fs - Floating Point Absolute Value
1448 * fmt -----
1449 * fd -----
1450 * fs -----
1465 * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
1466 * with 16-bit saturation
1471 * rt -----
1472 * rs -----
1487 * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
1488 * with 8-bit saturation
1493 * rt -----
1494 * rs -----
1509 * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
1515 * rt -----
1516 * rs -----
1536 * rt -----
1537 * rs -----
1558 * rt -----
1559 * rs -----
1576 * ADD.D fd, fs, ft - Floating Point Add
1581 * fmt -----
1582 * ft -----
1583 * fs -----
1584 * fd -----
1601 * ADD.S fd, fs, ft - Floating Point Add
1606 * fmt -----
1607 * ft -----
1608 * fs -----
1609 * fd -----
1631 * rt -----
1632 * rs -----
1653 * rt -----
1654 * rs -----
1673 * rt -----
1674 * rs -----
1693 * rt -----
1694 * rs -----
1713 * rt -----
1714 * rs -----
1733 * rt -----
1734 * rs -----
1756 * rt -----
1757 * rs -----
1776 * rt -----
1777 * rs -----
1793 * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
1797 * rt -----
1798 * s - ---
1817 * rt -----
1818 * rs -----
1819 * rd -----
1839 * rt -----
1840 * rs -----
1841 * rd -----
1856 * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
1861 * rt -----
1862 * rs -----
1863 * rd -----
1880 * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
1886 * rt -----
1887 * rs -----
1888 * rd -----
1905 * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
1910 * rt -----
1911 * rs -----
1912 * rd -----
1929 * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
1935 * rt -----
1936 * rs -----
1937 * rd -----
1954 * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
1960 * rt -----
1961 * rs -----
1962 * rd -----
1979 * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
1985 * rt -----
1986 * rs -----
1987 * rd -----
2004 * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
2010 * rt -----
2011 * rs -----
2012 * rd -----
2029 * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
2034 * rt -----
2035 * rs -----
2036 * rd -----
2053 * ADDU[16] rd3, rs3, rt3 -
2057 * rt3 ---
2058 * rs3 ---
2059 * rd3 ---
2081 * rt -----
2082 * rs -----
2083 * rd -----
2105 * rt -----
2106 * rs -----
2107 * rd -----
2122 * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
2127 * rt -----
2128 * rs -----
2129 * rd -----
2146 * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2151 * rt -----
2152 * rs -----
2153 * rd -----
2170 * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
2176 * rt -----
2177 * rs -----
2178 * rd -----
2195 * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2200 * rt -----
2201 * rs -----
2202 * rd -----
2219 * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2225 * rt -----
2226 * rs -----
2227 * rd -----
2244 * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2250 * rt -----
2251 * rs -----
2252 * rd -----
2268 * ADDWC rd, rt, rs - Add Word with Carry Bit
2273 * rt -----
2274 * rs -----
2275 * rd -----
2297 * rt -----
2298 * rs -----
2299 * rd -----
2314 * AND[16] rt3, rs3 -
2318 * rt3 ---
2319 * rs3 ---
2320 * eu ----
2340 * rt -----
2341 * rs -----
2342 * rd -----
2359 * ANDI rt, rs, u -
2363 * rt3 ---
2364 * rs3 ---
2365 * eu ----
2387 * rt -----
2388 * rs -----
2389 * rd -----
2410 * rt -----
2411 * rs -----
2412 * rd -----
2433 * rt -----
2434 * rs -----
2435 * rd -----
2456 * rt -----
2457 * rs -----
2458 * rd -----
2476 * rt -----
2477 * rs -----
2478 * rd -----
2496 * rt -----
2497 * rs -----
2498 * rd -----
2518 * rt -----
2519 * rs -----
2520 * rd -----
2541 * rt -----
2542 * rs -----
2543 * rd -----
2564 * rt -----
2565 * rs -----
2566 * rd -----
2584 * rt -----
2585 * rs -----
2586 * rd -----
2604 * rt -----
2605 * rs -----
2606 * rd -----
2626 * rt -----
2627 * rs -----
2628 * rd -----
2648 * rt -----
2649 * rs -----
2650 * rd -----
2669 * rt -----
2670 * rs -----
2671 * rd -----
2690 * rt -----
2691 * rs -----
2692 * rd -----
2714 * rt -----
2715 * rs -----
2716 * rd -----
2738 * rt -----
2739 * rs -----
2740 * rd -----
2761 * rt -----
2762 * rs -----
2763 * rd -----
2783 * rt -----
2784 * rs -----
2785 * rd -----
2807 * rt -----
2808 * rs -----
2809 * rd -----
2830 * rt -----
2831 * rs -----
2832 * rd -----
2853 * rt -----
2854 * rs -----
2855 * rd -----
2877 * rt -----
2878 * rs -----
2879 * rd -----
2901 * rt -----
2902 * rs -----
2903 * rd -----
2924 * rt -----
2925 * rs -----
2926 * rd -----
2947 * rt -----
2948 * rs -----
2949 * rd -----
2971 * rt -----
2972 * rs -----
2973 * rd -----
2995 * rt -----
2996 * rs -----
2997 * rd -----
3019 * rt -----
3020 * rs -----
3021 * rd -----
3042 * rt -----
3043 * rs -----
3044 * rd -----
3059 * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in
3065 * s[13:1] -------------
3066 * s[14] -
3084 * rt -----
3085 * rs -----
3086 * rd -----
3098 * BREAK code - Break. Cause a Breakpoint exception
3103 * rt -----
3104 * rs -----
3105 * rd -----
3122 * rt -----
3123 * rs -----
3124 * rd -----
3142 * rt -----
3143 * rs -----
3144 * rd -----
3165 * rt -----
3166 * rs -----
3167 * rd -----
3188 * rt -----
3189 * rs -----
3190 * rd -----
3210 * rt -----
3211 * rs -----
3212 * rd -----
3232 * rt -----
3233 * rs -----
3234 * rd -----
3254 * rt -----
3255 * rs -----
3256 * rd -----
3276 * rt -----
3277 * rs -----
3278 * rd -----
3297 * rt -----
3298 * rs -----
3299 * rd -----
3318 * rt -----
3319 * rs -----
3320 * rd -----
3340 * rt -----
3341 * rs -----
3342 * rd -----
3362 * rt -----
3363 * rs -----
3364 * rd -----
3384 * rt -----
3385 * rs -----
3386 * rd -----
3406 * rt -----
3407 * rs -----
3408 * rd -----
3430 * rt -----
3431 * rs -----
3432 * rd -----
3454 * rt -----
3455 * rs -----
3456 * rd -----
3473 * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values
3478 * rt -----
3479 * rs -----
3499 * rt -----
3500 * rs -----
3501 * rd -----
3523 * rt -----
3524 * rs -----
3525 * rd -----
3542 * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values
3547 * rt -----
3548 * rs -----
3568 * rt -----
3569 * rs -----
3570 * rd -----
3592 * rt -----
3593 * rs -----
3594 * rd -----
3611 * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values
3616 * rt -----
3617 * rs -----
3637 * rt -----
3638 * rs -----
3639 * rd -----
3661 * rt -----
3662 * rs -----
3663 * rd -----
3685 * rt -----
3686 * rs -----
3687 * rd -----
3709 * rt -----
3710 * rs -----
3711 * rd -----
3733 * rt -----
3734 * rs -----
3735 * rd -----
3757 * rt -----
3758 * rs -----
3759 * rd -----
3781 * rt -----
3782 * rs -----
3783 * rd -----
3805 * rt -----
3806 * rs -----
3807 * rd -----
3829 * rt -----
3830 * rs -----
3831 * rd -----
3853 * rt -----
3854 * rs -----
3855 * rd -----
3877 * rt -----
3878 * rs -----
3879 * rd -----
3901 * rt -----
3902 * rs -----
3903 * rd -----
3925 * rt -----
3926 * rs -----
3927 * rd -----
3949 * rt -----
3950 * rs -----
3951 * rd -----
3973 * rt -----
3974 * rs -----
3975 * rd -----
3997 * rt -----
3998 * rs -----
3999 * rd -----
4021 * rt -----
4022 * rs -----
4023 * rd -----
4045 * rt -----
4046 * rs -----
4047 * rd -----
4069 * rt -----
4070 * rs -----
4071 * rd -----
4093 * rt -----
4094 * rs -----
4095 * rd -----
4117 * rt -----
4118 * rs -----
4119 * rd -----
4141 * rt -----
4142 * rs -----
4143 * rd -----
4165 * rt -----
4166 * rs -----
4167 * rd -----
4189 * rt -----
4190 * rs -----
4191 * rd -----
4213 * rt -----
4214 * rs -----
4215 * rd -----
4237 * rt -----
4238 * rs -----
4239 * rd -----
4261 * rt -----
4262 * rs -----
4263 * rd -----
4285 * rt -----
4286 * rs -----
4287 * rd -----
4309 * rt -----
4310 * rs -----
4311 * rd -----
4333 * rt -----
4334 * rs -----
4335 * rd -----
4357 * rt -----
4358 * rs -----
4359 * rd -----
4381 * rt -----
4382 * rs -----
4383 * rd -----
4405 * rt -----
4406 * rs -----
4407 * rd -----
4429 * rt -----
4430 * rs -----
4431 * rd -----
4453 * rt -----
4454 * rs -----
4455 * rd -----
4477 * rt -----
4478 * rs -----
4479 * rd -----
4501 * rt -----
4502 * rs -----
4503 * rd -----
4520 * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4526 * rt -----
4527 * rs -----
4528 * rd -----
4545 * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of
4551 * rt -----
4552 * rs -----
4553 * rd -----
4570 * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4576 * rt -----
4577 * rs -----
4578 * rd -----
4595 * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4601 * rt -----
4602 * rs -----
4603 * rd -----
4620 * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned
4626 * rt -----
4627 * rs -----
4628 * rd -----
4645 * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned
4651 * rt -----
4652 * rs -----
4653 * rd -----
4670 * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4676 * rt -----
4677 * rs -----
4692 * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned
4698 * rt -----
4699 * rs -----
4714 * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned
4720 * rt -----
4721 * rs -----
4741 * rt -----
4742 * rs -----
4743 * rd -----
4760 * rt -----
4761 * rs -----
4762 * rd -----
4781 * rt -----
4782 * rs -----
4783 * rd -----
4802 * rt -----
4803 * rs -----
4804 * rd -----
4824 * rt -----
4825 * rs -----
4826 * rd -----
4846 * rt -----
4847 * rs -----
4848 * rd -----
4868 * rt -----
4869 * rs -----
4870 * rd -----
4890 * rt -----
4891 * rs -----
4892 * rd -----
4912 * rt -----
4913 * rs -----
4914 * rd -----
4934 * rt -----
4935 * rs -----
4936 * rd -----
4956 * rt -----
4957 * rs -----
4958 * rd -----
4978 * rt -----
4979 * rs -----
4980 * rd -----
5000 * rt -----
5001 * rs -----
5002 * rd -----
5022 * rt -----
5023 * rs -----
5024 * rd -----
5044 * rt -----
5045 * rs -----
5046 * rd -----
5066 * rt -----
5067 * rs -----
5068 * rd -----
5087 * rt -----
5088 * rs -----
5089 * rd -----
5111 * rt -----
5112 * rs -----
5113 * rd -----
5134 * rt -----
5135 * rs -----
5136 * rd -----
5158 * rt -----
5159 * rs -----
5160 * rd -----
5182 * rt -----
5183 * rs -----
5184 * rd -----
5204 * rt -----
5205 * rs -----
5206 * rd -----
5226 * rt -----
5227 * rs -----
5228 * rd -----
5250 * rt -----
5251 * rs -----
5252 * rd -----
5274 * rt -----
5275 * rs -----
5276 * rd -----
5292 * rt -----
5293 * rs -----
5294 * rd -----
5318 * rt -----
5319 * rs -----
5320 * rd -----
5344 * rt -----
5345 * rs -----
5346 * rd -----
5370 * rt -----
5371 * rs -----
5372 * rd -----
5383 /* !!!!!!!!!! - no conversion function */ in DINSM()
5397 * rt -----
5398 * rs -----
5399 * rd -----
5410 /* !!!!!!!!!! - no conversion function */ in DINS()
5424 * rt -----
5425 * rs -----
5426 * rd -----
5437 /* !!!!!!!!!! - no conversion function */ in DINSU()
5451 * rt -----
5452 * rs -----
5453 * rd -----
5471 * rt -----
5472 * rs -----
5473 * rd -----
5495 * rt -----
5496 * rs -----
5497 * rd -----
5519 * rt -----
5520 * rs -----
5521 * rd -----
5543 * rt -----
5544 * rs -----
5545 * rd -----
5567 * rt -----
5568 * rs -----
5569 * rd -----
5592 * rt -----
5593 * rs -----
5594 * rd -----
5613 * rt -----
5614 * rs -----
5615 * rd -----
5636 * rt -----
5637 * rs -----
5638 * rd -----
5658 * rt -----
5659 * rs -----
5660 * rd -----
5679 * rt -----
5680 * rs -----
5681 * rd -----
5702 * rt -----
5703 * rs -----
5704 * rd -----
5726 * rt -----
5727 * rs -----
5728 * rd -----
5750 * rt -----
5751 * rs -----
5752 * rd -----
5773 * rt -----
5774 * rs -----
5775 * rd -----
5795 * rt -----
5796 * rs -----
5797 * rd -----
5816 * rt -----
5817 * rs -----
5818 * rd -----
5839 * rt -----
5840 * rs -----
5841 * rd -----
5859 * rt -----
5860 * rs -----
5861 * rd -----
5883 * rt -----
5884 * rs -----
5885 * rd -----
5907 * rt -----
5908 * rs -----
5909 * rd -----
5931 * rt -----
5932 * rs -----
5933 * rd -----
5950 * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on
5956 * rt -----
5957 * rs -----
5958 * ac --
5980 * rt -----
5981 * rs -----
5982 * rd -----
6004 * rt -----
6005 * rs -----
6006 * rd -----
6028 * rt -----
6029 * rs -----
6030 * rd -----
6052 * rt -----
6053 * rs -----
6054 * rd -----
6076 * rt -----
6077 * rs -----
6078 * rd -----
6100 * rt -----
6101 * rs -----
6102 * rd -----
6124 * rt -----
6125 * rs -----
6126 * rd -----
6148 * rt -----
6149 * rs -----
6150 * rd -----
6172 * rt -----
6173 * rs -----
6174 * rd -----
6196 * rt -----
6197 * rs -----
6198 * rd -----
6220 * rt -----
6221 * rs -----
6222 * rd -----
6244 * rt -----
6245 * rs -----
6246 * rd -----
6268 * rt -----
6269 * rs -----
6270 * rd -----
6292 * rt -----
6293 * rs -----
6294 * rd -----
6316 * rt -----
6317 * rs -----
6318 * rd -----
6335 * DROTR -
6340 * rt -----
6341 * rs -----
6342 * rd -----
6358 * DROTR[32] -
6363 * rt -----
6364 * rs -----
6365 * shift -----
6386 * rt -----
6387 * rs -----
6388 * rd -----
6410 * rt -----
6411 * rs -----
6412 * rd -----
6430 * DSLL -
6435 * rt -----
6436 * rs -----
6437 * shift -----
6453 * DSLL[32] -
6458 * rt -----
6459 * rs -----
6460 * shift -----
6481 * rt -----
6482 * rs -----
6483 * rd -----
6500 * DSRA -
6505 * rt -----
6506 * rs -----
6507 * shift -----
6523 * DSRA[32] -
6528 * rt -----
6529 * rs -----
6530 * shift -----
6551 * rt -----
6552 * rs -----
6553 * rd -----
6570 * DSRL -
6575 * rt -----
6576 * rs -----
6577 * shift -----
6593 * DSRL[32] -
6598 * rt -----
6599 * rs -----
6600 * shift -----
6621 * rt -----
6622 * rs -----
6623 * rd -----
6645 * rt -----
6646 * rs -----
6647 * rd -----
6669 * rt -----
6670 * rs -----
6671 * rd -----
6693 * rt -----
6694 * rs -----
6695 * rd -----
6713 * rt -----
6714 * rs -----
6715 * rd -----
6733 * rt -----
6734 * rs -----
6735 * rd -----
6751 * rt -----
6752 * rs -----
6753 * rd -----
6771 * rt -----
6772 * rs -----
6773 * rd -----
6791 * rt -----
6792 * rs -----
6793 * rd -----
6809 * rt -----
6810 * rs -----
6811 * rd -----
6827 * rt -----
6828 * rs -----
6829 * rd -----
6847 * rt -----
6848 * rs -----
6849 * rd -----
6867 * rt -----
6868 * rs -----
6869 * rd -----
6893 * rt -----
6894 * rs -----
6895 * rd -----
6918 * rt -----
6919 * rs -----
6920 * rd -----
6943 * rt -----
6944 * rs -----
6945 * rd -----
6966 * rt -----
6967 * rs -----
6968 * rd -----
6990 * rt -----
6991 * rs -----
6992 * rd -----
7013 * rt -----
7014 * rs -----
7015 * rd -----
7032 * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR
7038 * rt -----
7039 * shift -----
7040 * ac --
7056 * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR
7062 * rt -----
7063 * shift -----
7064 * ac --
7080 * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator
7086 * rt -----
7087 * shift -----
7088 * ac --
7104 * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR
7110 * rt -----
7111 * shift -----
7112 * ac --
7128 * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable
7134 * rt -----
7135 * rs -----
7136 * ac --
7153 * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable
7159 * rt -----
7160 * rs -----
7161 * ac --
7178 * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from
7184 * rt -----
7185 * rs -----
7186 * ac --
7203 * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable
7209 * rt -----
7210 * rs -----
7211 * ac --
7228 * EXTW - Extract Word
7233 * rt -----
7234 * rs -----
7235 * rd -----
7236 * shift -----
7259 * rt -----
7260 * rs -----
7261 * rd -----
7281 * rt -----
7282 * rs -----
7283 * rd -----
7303 * rt -----
7304 * rs -----
7305 * rd -----
7325 * rt -----
7326 * rs -----
7327 * rd -----
7347 * rt -----
7348 * rs -----
7349 * rd -----
7371 * rt -----
7372 * rs -----
7373 * rd -----
7390 * rt -----
7391 * rs -----
7392 * rd -----
7409 * rt -----
7410 * rs -----
7411 * rd -----
7422 /* !!!!!!!!!! - no conversion function */ in INS()
7431 * [DSP] INSV rt, rs - Insert bit field variable
7436 * rt -----
7437 * rs -----
7457 * rt -----
7458 * rs -----
7459 * rd -----
7475 * rt -----
7476 * rs -----
7477 * rd -----
7495 * rt -----
7496 * rs -----
7497 * rd -----
7517 * rt -----
7518 * rs -----
7519 * rd -----
7539 * rt -----
7540 * rs -----
7541 * rd -----
7559 * rt -----
7560 * rs -----
7561 * rd -----
7582 * rt -----
7583 * rs -----
7584 * rd -----
7603 * rt -----
7604 * rs -----
7605 * rd -----
7626 * rt -----
7627 * rs -----
7628 * rd -----
7649 * rt -----
7650 * rs -----
7651 * rd -----
7672 * rt -----
7673 * rs -----
7674 * rd -----
7695 * rt -----
7696 * rs -----
7697 * rd -----
7716 * rt -----
7717 * rs -----
7718 * rd -----
7739 * rt -----
7740 * rs -----
7741 * rd -----
7762 * rt -----
7763 * rs -----
7764 * rd -----
7785 * rt -----
7786 * rs -----
7787 * rd -----
7809 * rt -----
7810 * rs -----
7811 * rd -----
7833 * rt -----
7834 * rs -----
7835 * rd -----
7854 * rt -----
7855 * rs -----
7856 * rd -----
7877 * rt -----
7878 * rs -----
7879 * rd -----
7900 * rt -----
7901 * rs -----
7902 * rd -----
7921 * rt -----
7922 * rs -----
7923 * rd -----
7944 * rt -----
7945 * rs -----
7946 * rd -----
7967 * rt -----
7968 * rs -----
7969 * rd -----
7991 * rt -----
7992 * rs -----
7993 * rd -----
8015 * rt -----
8016 * rs -----
8017 * rd -----
8038 * rt -----
8039 * rs -----
8040 * rd -----
8064 * rt -----
8065 * rs -----
8066 * rd -----
8086 * rt -----
8087 * rs -----
8088 * rd -----
8110 * rt -----
8111 * rs -----
8112 * rd -----
8134 * rt -----
8135 * rs -----
8136 * rd -----
8157 * rt -----
8158 * rs -----
8159 * rd -----
8178 * rt -----
8179 * rs -----
8180 * rd -----
8201 * rt -----
8202 * rs -----
8203 * rd -----
8224 * rt -----
8225 * rs -----
8226 * rd -----
8247 * rt -----
8248 * rs -----
8249 * rd -----
8270 * rt -----
8271 * rs -----
8272 * rd -----
8291 * rt -----
8292 * rs -----
8293 * rd -----
8314 * rt -----
8315 * rs -----
8316 * rd -----
8337 * rt -----
8338 * rs -----
8339 * rd -----
8360 * rt -----
8361 * rs -----
8362 * rd -----
8384 * rt -----
8385 * rs -----
8386 * rd -----
8408 * rt -----
8409 * rs -----
8410 * rd -----
8432 * rt -----
8433 * rs -----
8434 * rd -----
8456 * rt -----
8457 * rs -----
8458 * rd -----
8478 * rt -----
8479 * rs -----
8480 * rd -----
8499 * rt -----
8500 * rs -----
8501 * rd -----
8522 * rt -----
8523 * rs -----
8524 * rd -----
8545 * rt -----
8546 * rs -----
8547 * rd -----
8569 * rt -----
8570 * rs -----
8571 * rd -----
8592 * rt -----
8593 * rs -----
8594 * rd -----
8616 * rt -----
8617 * rs -----
8618 * rd -----
8640 * rt -----
8641 * rs -----
8642 * rd -----
8665 * rt -----
8666 * rs -----
8667 * rd -----
8686 * rt -----
8687 * rs -----
8688 * rd -----
8709 * rt -----
8710 * rs -----
8711 * rd -----
8732 * rt -----
8733 * rs -----
8734 * rd -----
8753 * rt -----
8754 * rs -----
8755 * rd -----
8774 * rt -----
8775 * rs -----
8776 * rd -----
8797 * rt -----
8798 * rs -----
8799 * rd -----
8818 * rt -----
8819 * rs -----
8820 * rd -----
8841 * rt -----
8842 * rs -----
8843 * rd -----
8862 * rt -----
8863 * rs -----
8864 * rd -----
8885 * rt -----
8886 * rs -----
8887 * rd -----
8908 * rt -----
8909 * rs -----
8910 * rd -----
8932 * rt -----
8933 * rs -----
8934 * rd -----
8956 * rt -----
8957 * rs -----
8958 * rd -----
8979 * rt -----
8980 * rs -----
8981 * rd -----
9002 * rt -----
9003 * rs -----
9004 * rd -----
9028 * rt -----
9029 * rs -----
9030 * rd -----
9050 * rt -----
9051 * rs -----
9052 * rd -----
9071 * rt -----
9072 * rs -----
9073 * rd -----
9094 * rt -----
9095 * rs -----
9096 * rd -----
9117 * rt -----
9118 * rs -----
9119 * rd -----
9141 * rt -----
9142 * rs -----
9143 * rd -----
9165 * rt -----
9166 * rs -----
9167 * rd -----
9189 * rt -----
9190 * rs -----
9191 * rd -----
9213 * rt -----
9214 * rs -----
9215 * rd -----
9232 * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
9238 * rt -----
9239 * rs -----
9240 * rd -----
9262 * rt -----
9263 * rs -----
9264 * rd -----
9286 * rt -----
9287 * rs -----
9288 * rd -----
9305 * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
9311 * rt -----
9312 * rs -----
9313 * rd -----
9330 * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
9336 * rt -----
9337 * rs -----
9338 * rd -----
9355 * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
9361 * rt -----
9362 * rs -----
9363 * rd -----
9380 * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
9386 * rt -----
9387 * rs -----
9388 * rd -----
9405 * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
9411 * rt -----
9412 * rs -----
9413 * rd -----
9435 * rt -----
9436 * rs -----
9437 * rd -----
9459 * rt -----
9460 * rs -----
9461 * rd -----
9483 * rt -----
9484 * rs -----
9485 * rd -----
9507 * rt -----
9508 * rs -----
9509 * rd -----
9531 * rt -----
9532 * rs -----
9533 * rd -----
9554 * rt -----
9555 * rs -----
9556 * rd -----
9576 * rt -----
9577 * rs -----
9578 * rd -----
9597 * rt -----
9598 * rs -----
9599 * rd -----
9620 * rt -----
9621 * rs -----
9622 * rd -----
9643 * rt -----
9644 * rs -----
9645 * rd -----
9665 * rt -----
9666 * rs -----
9667 * rd -----
9686 * rt -----
9687 * rs -----
9688 * rd -----
9704 * [DSP] MFHI rs, ac - Move from HI register
9709 * rt -----
9710 * ac --
9730 * rt -----
9731 * rs -----
9732 * rd -----
9749 * [DSP] MFLO rs, ac - Move from HI register
9754 * rt -----
9755 * ac --
9775 * rt -----
9776 * rs -----
9777 * rd -----
9799 * rt -----
9800 * rs -----
9801 * rd -----
9823 * rt -----
9824 * rs -----
9825 * rd -----
9847 * rt -----
9848 * rs -----
9849 * rd -----
9871 * rt -----
9872 * rs -----
9873 * rd -----
9895 * rt -----
9896 * rs -----
9897 * rd -----
9914 * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
9919 * rt -----
9920 * rs -----
9921 * rd -----
9943 * rt -----
9944 * rs -----
9945 * rd -----
9967 * rt -----
9968 * rs -----
9969 * rd -----
9989 * rt -----
9990 * rs -----
9991 * rd -----
10011 * rt -----
10012 * rs -----
10013 * rd -----
10035 * rt -----
10036 * rs -----
10037 * rd -----
10047 /* !!!!!!!!!! - no conversion function */ in MOVEP()
10062 * rt -----
10063 * rs -----
10064 * rd -----
10076 /* !!!!!!!!!! - no conversion function */ in MOVEP_REV_()
10084 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10089 * rt -----
10090 * rs -----
10091 * rd -----
10106 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10111 * rt -----
10112 * rs -----
10113 * rd -----
10130 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10135 * rt -----
10136 * rs -----
10137 * rd -----
10154 * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
10159 * rt -----
10160 * rs -----
10161 * ac --
10178 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10183 * rt -----
10184 * rs -----
10185 * rd -----
10202 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10207 * rt -----
10208 * rs -----
10209 * rd -----
10226 * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
10231 * rt -----
10232 * rs -----
10233 * ac --
10250 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10255 * rt -----
10256 * rs -----
10257 * rd -----
10273 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10278 * rt -----
10279 * rs -----
10280 * rd -----
10295 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10300 * rt -----
10301 * rs -----
10302 * rd -----
10316 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10321 * rt -----
10322 * rs -----
10323 * rd -----
10339 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10344 * rt -----
10345 * rs -----
10346 * rd -----
10362 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10367 * rt -----
10368 * rs -----
10369 * rd -----
10384 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10389 * rt -----
10390 * rs -----
10391 * rd -----
10405 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10410 * rt -----
10411 * rs -----
10412 * rd -----
10428 * [DSP] MTHI rs, ac - Move to HI register
10433 * rs -----
10434 * ac --
10449 * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
10454 * rs -----
10455 * ac --
10470 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10475 * rt -----
10476 * rs -----
10477 * rd -----
10494 * [DSP] MTLO rs, ac - Move to LO register
10499 * rs -----
10500 * ac --
10515 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10520 * rt -----
10521 * rs -----
10522 * rd -----
10539 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10544 * rt -----
10545 * rs -----
10546 * rd -----
10563 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10568 * rt -----
10569 * rs -----
10570 * rd -----
10587 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10592 * rt -----
10593 * rs -----
10594 * rd -----
10611 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10616 * rt -----
10617 * rs -----
10618 * rd -----
10633 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10638 * rt -----
10639 * rs -----
10640 * rd -----
10657 * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
10663 * rt -----
10664 * rs -----
10665 * rd -----
10682 * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
10688 * rt -----
10689 * rs -----
10690 * rd -----
10707 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10712 * rt -----
10713 * rs -----
10714 * rd -----
10731 * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords
10737 * rt -----
10738 * rs -----
10739 * rd -----
10756 * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords
10762 * rt -----
10763 * rs -----
10764 * rd -----
10781 * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes
10787 * rt -----
10788 * rs -----
10789 * rd -----
10806 * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes
10812 * rt -----
10813 * rs -----
10814 * rd -----
10831 * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords
10837 * rt -----
10838 * rs -----
10839 * rd -----
10856 * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size
10862 * rt -----
10863 * rs -----
10864 * rd -----
10881 * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size
10887 * rt -----
10888 * rs -----
10889 * rd -----
10906 * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product
10912 * rt -----
10913 * rs -----
10914 * rd -----
10931 * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword
10937 * rt -----
10938 * rs -----
10939 * ac --
10956 * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional
10962 * rt -----
10963 * rs -----
10964 * ac --
10981 * [DSP] MULT ac, rs, rt - Multiply word
10986 * rt -----
10987 * rs -----
10988 * ac --
11005 * [DSP] MULTU ac, rs, rt - Multiply unsigned word
11010 * rt -----
11011 * rs -----
11012 * ac --
11029 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11034 * rt -----
11035 * rs -----
11036 * rd -----
11053 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11058 * rt -----
11059 * rs -----
11060 * rd -----
11075 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11080 * rt -----
11081 * rs -----
11082 * rd -----
11097 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11102 * rt -----
11103 * rs -----
11104 * rd -----
11115 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11120 * rt -----
11121 * rs -----
11122 * rd -----
11133 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11138 * rt -----
11139 * rs -----
11140 * rd -----
11157 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11162 * rt -----
11163 * rs -----
11164 * rd -----
11179 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11184 * rt -----
11185 * rs -----
11186 * rd -----
11201 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11206 * rt -----
11207 * rs -----
11208 * rd -----
11225 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11230 * rt -----
11231 * rs -----
11232 * rd -----
11248 * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
11254 * rt -----
11255 * rs -----
11256 * rd -----
11273 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11278 * rt -----
11279 * rs -----
11280 * rd -----
11291 * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
11297 * rt -----
11298 * rs -----
11299 * rd -----
11316 * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
11322 * rt -----
11323 * rs -----
11324 * rd -----
11341 * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
11347 * rt -----
11348 * rs -----
11349 * rd -----
11364 * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
11370 * rt -----
11371 * rs -----
11372 * rd -----
11387 * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
11388 * left-alternate elements of a quad byte vector
11393 * rt -----
11394 * rs -----
11395 * rd -----
11410 * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
11416 * rt -----
11417 * rs -----
11418 * rd -----
11433 * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
11434 * right-alternate elements of a quad byte vector
11439 * rt -----
11440 * rs -----
11441 * rd -----
11456 * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
11462 * rt -----
11463 * rs -----
11464 * rd -----
11479 * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
11480 * left-alternate elements of a quad byte vector to four unsigned
11486 * rt -----
11487 * rs -----
11488 * rd -----
11503 * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
11509 * rt -----
11510 * rs -----
11511 * rd -----
11526 * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
11527 * right-alternate elements of a quad byte vector to form four
11533 * rt -----
11534 * rs -----
11535 * rd -----
11550 * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
11556 * rt -----
11557 * rs -----
11558 * rd -----
11573 * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer
11579 * rt -----
11580 * rs -----
11581 * rd -----
11598 * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer
11604 * rt -----
11605 * rs -----
11606 * rd -----
11622 * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer
11628 * rt -----
11629 * rs -----
11630 * rd -----
11646 * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional
11652 * rt -----
11653 * rs -----
11654 * rd -----
11671 * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional
11677 * rt -----
11678 * rs -----
11679 * rd -----
11696 * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional
11702 * rt -----
11703 * rs -----
11704 * rd -----
11721 * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional
11727 * rt -----
11728 * rs -----
11729 * rd -----
11751 * rt -----
11752 * rs -----
11753 * rd -----
11774 * rt -----
11775 * rs -----
11776 * rd -----
11797 * rt -----
11798 * rs -----
11799 * rd -----
11815 * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB
11820 * rt -----
11821 * rs -----
11822 * rd -----
11838 * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes
11843 * rt -----
11844 * rs -----
11859 * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR
11864 * rt -----
11865 * mask -------
11884 * rt -----
11885 * rs -----
11886 * rd -----
11907 * rt -----
11908 * rs -----
11909 * rd -----
11929 * rt -----
11930 * rs -----
11931 * rd -----
11951 * rt -----
11952 * rs -----
11953 * rd -----
11968 * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element
11974 * rt -----
11975 * s ----------
11989 * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element
11995 * rt -----
11996 * u --------
12010 * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element
12016 * rt -----
12017 * rs -----
12032 * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions
12037 * rt -----
12038 * rs -----
12058 * rt -----
12059 * rs -----
12060 * rd -----
12081 * rt -----
12082 * rs -----
12083 * rd -----
12103 * rt -----
12104 * rs -----
12105 * rd -----
12127 * rt -----
12128 * rs -----
12129 * rd -----
12148 * rt -----
12149 * rs -----
12150 * rd -----
12170 * rt -----
12171 * rs -----
12172 * rd -----
12192 * rt -----
12193 * rs -----
12194 * rd -----
12215 * rt -----
12216 * rs -----
12217 * rd -----
12239 * rt -----
12240 * rs -----
12241 * rd -----
12265 * rt -----
12266 * rs -----
12267 * rd -----
12287 * rt -----
12288 * rs -----
12289 * rd -----
12309 * rt -----
12310 * rs -----
12311 * rd -----
12331 * rt -----
12332 * rs -----
12333 * rd -----
12353 * rt -----
12354 * rs -----
12355 * rd -----
12375 * rt -----
12376 * rs -----
12377 * rd -----
12397 * rt -----
12398 * rs -----
12399 * rd -----
12419 * rt -----
12420 * rs -----
12421 * rd -----
12442 * rt -----
12443 * rs -----
12444 * rd -----
12462 * rt -----
12463 * rs -----
12464 * rd -----
12485 * rt -----
12486 * rs -----
12487 * rd -----
12506 * rt -----
12507 * rs -----
12508 * rd -----
12529 * rt -----
12530 * rs -----
12531 * rd -----
12552 * rt -----
12553 * rs -----
12554 * rd -----
12575 * rt -----
12576 * rs -----
12577 * rd -----
12599 * rt -----
12600 * rs -----
12601 * rd -----
12622 * rt -----
12623 * rs -----
12624 * rd -----
12645 * rt -----
12646 * rs -----
12647 * rd -----
12669 * rt -----
12670 * rs -----
12671 * rd -----
12692 * rt -----
12693 * rs -----
12694 * rd -----
12716 * rt -----
12717 * rs -----
12718 * rd -----
12740 * rt -----
12741 * rs -----
12742 * rd -----
12761 * rt -----
12762 * rs -----
12763 * rd -----
12784 * rt -----
12785 * rs -----
12786 * rd -----
12807 * rt -----
12808 * rs -----
12809 * rd -----
12826 * rt -----
12827 * rs -----
12828 * rd -----
12845 * rt -----
12846 * rs -----
12847 * rd -----
12866 * rt -----
12867 * rs -----
12868 * rd -----
12889 * rt -----
12890 * rs -----
12891 * rd -----
12912 * rt -----
12913 * rs -----
12914 * rd -----
12936 * rt -----
12937 * rs -----
12938 * rd -----
12960 * rt -----
12961 * rs -----
12962 * rd -----
12983 * rt -----
12984 * rs -----
12985 * rd -----
13009 * rt -----
13010 * rs -----
13011 * rd -----
13031 * rt -----
13032 * rs -----
13033 * rd -----
13055 * rt -----
13056 * rs -----
13057 * rd -----
13079 * rt -----
13080 * rs -----
13081 * rd -----
13101 * rt -----
13102 * rs -----
13103 * rd -----
13123 * rt -----
13124 * rs -----
13125 * rd -----
13147 * rt -----
13148 * rs -----
13149 * rd -----
13171 * rt -----
13172 * rs -----
13173 * rd -----
13195 * rt -----
13196 * rs -----
13197 * rd -----
13219 * rt -----
13220 * rs -----
13221 * rd -----
13243 * rt -----
13244 * rs -----
13245 * rd -----
13267 * rt -----
13268 * rs -----
13269 * rd -----
13290 * rt -----
13291 * rs -----
13292 * rd -----
13313 * rt -----
13314 * rs -----
13315 * rd -----
13334 * rt -----
13335 * rs -----
13336 * rd -----
13357 * rt -----
13358 * rs -----
13359 * rd -----
13380 * rt -----
13381 * rs -----
13382 * rd -----
13398 * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in
13404 * shift ------
13405 * ac --
13419 * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result
13425 * rs -----
13426 * ac --
13441 * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords
13446 * rt -----
13447 * rs -----
13448 * sa ----
13464 * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes
13469 * rt -----
13470 * rs -----
13471 * sa ---
13487 * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords
13493 * rt -----
13494 * rs -----
13495 * sa ----
13511 * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation
13516 * rt -----
13517 * rs -----
13518 * sa -----
13534 * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13540 * rt -----
13541 * rs -----
13542 * rd -----
13559 * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes
13564 * rt -----
13565 * rs -----
13566 * rd -----
13583 * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13589 * rt -----
13590 * rs -----
13591 * rd -----
13608 * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word
13613 * rt -----
13614 * rs -----
13615 * rd -----
13637 * rt -----
13638 * rs -----
13639 * rd -----
13660 * rt -----
13661 * rs -----
13662 * rd -----
13683 * rt -----
13684 * rs -----
13685 * rd -----
13706 * rt -----
13707 * rs -----
13708 * rd -----
13729 * rt -----
13730 * rs -----
13731 * rd -----
13752 * rt -----
13753 * rs -----
13754 * rd -----
13776 * rt -----
13777 * rs -----
13778 * rd -----
13800 * rt -----
13801 * rs -----
13802 * rd -----
13824 * rt -----
13825 * rs -----
13826 * rd -----
13848 * rt -----
13849 * rs -----
13850 * rd -----
13867 * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords
13872 * rt -----
13873 * rs -----
13874 * sa ----
13890 * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes
13895 * rt -----
13896 * rs -----
13897 * sa ---
13913 * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of
13919 * rt -----
13920 * rs -----
13921 * rd -----
13938 * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes
13943 * rt -----
13944 * rs -----
13945 * rd -----
13967 * rt -----
13968 * rs -----
13969 * rd -----
13991 * rt -----
13992 * rs -----
13993 * rd -----
14015 * rt -----
14016 * rs -----
14017 * rd -----
14034 * rt -----
14035 * rs -----
14036 * rd -----
14058 * rt -----
14059 * rs -----
14060 * rd -----
14081 * rt -----
14082 * rs -----
14083 * rd -----
14105 * rt -----
14106 * rs -----
14107 * rd -----
14129 * rt -----
14130 * rs -----
14131 * rd -----
14152 * rt -----
14153 * rs -----
14154 * rd -----
14175 * rt -----
14176 * rs -----
14177 * rd -----
14199 * rt -----
14200 * rs -----
14201 * rd -----
14223 * rt -----
14224 * rs -----
14225 * rd -----
14242 * rt -----
14243 * rs -----
14244 * rd -----
14264 * rt -----
14265 * rs -----
14266 * rd -----
14281 * SRA rd, rt, sa - Shift Word Right Arithmetic
14286 * rt -----
14287 * rd -----
14288 * sa -----
14304 * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14309 * rs -----
14310 * rt -----
14311 * rd -----
14333 * rs -----
14334 * rt -----
14335 * rd -----
14357 * rt -----
14358 * rs -----
14359 * rd -----
14380 * rt -----
14381 * rs -----
14382 * rd -----
14404 * rt -----
14405 * rs -----
14406 * rd -----
14428 * rt -----
14429 * rs -----
14430 * rd -----
14452 * rt -----
14453 * rs -----
14454 * rd -----
14476 * rt -----
14477 * rs -----
14478 * rd -----
14495 * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14501 * rt -----
14502 * rs -----
14503 * rd -----
14520 * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift
14526 * rt -----
14527 * rs -----
14528 * rd -----
14545 * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14551 * rt -----
14552 * rs -----
14553 * rd -----
14570 * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14576 * rt -----
14577 * rs -----
14578 * rd -----
14595 * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift
14601 * rt -----
14602 * rs -----
14603 * rd -----
14620 * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to
14626 * rt -----
14627 * rs -----
14628 * rd -----
14645 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14650 * rt -----
14651 * rs -----
14652 * rd -----
14669 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14674 * rt -----
14675 * rs -----
14676 * rd -----
14693 * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
14698 * rt -----
14699 * rs -----
14700 * rd -----
14717 * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
14722 * rt -----
14723 * rs -----
14724 * rd -----
14741 * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
14742 * 8-bit saturation
14747 * rt -----
14748 * rs -----
14749 * rd -----
14766 * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
14767 * 8-bit saturation
14772 * rt -----
14773 * rs -----
14774 * rd -----
14791 * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
14797 * rt -----
14798 * rs -----
14799 * rd -----
14816 * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
14822 * rt -----
14823 * rs -----
14824 * rd -----
14841 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14846 * rt -----
14847 * rs -----
14848 * rd -----
14864 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14869 * rt -----
14870 * rs -----
14871 * rd -----
14887 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14892 * rt -----
14893 * rs -----
14894 * rd -----
14908 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14913 * rt -----
14914 * rs -----
14915 * rd -----
14929 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14934 * rt -----
14935 * rs -----
14936 * rd -----
14952 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14957 * rt -----
14958 * rs -----
14959 * rd -----
14973 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14978 * rt -----
14979 * rs -----
14980 * rd -----
14996 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15001 * rt -----
15002 * rs -----
15003 * rd -----
15017 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15022 * rt -----
15023 * rs -----
15024 * rd -----
15040 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15045 * rt -----
15046 * rs -----
15047 * rd -----
15063 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15068 * rt -----
15069 * rs -----
15070 * rd -----
15087 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15092 * rt -----
15093 * rs -----
15094 * rd -----
15111 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15116 * rt -----
15117 * rs -----
15118 * rd -----
15134 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15139 * rt -----
15140 * rs -----
15141 * rd -----
15157 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15162 * rt -----
15163 * rs -----
15164 * rd -----
15183 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15188 * rt -----
15189 * rs -----
15190 * rd -----
15205 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15210 * rt -----
15211 * rs -----
15212 * rd -----
15229 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15234 * rt -----
15235 * rs -----
15236 * rd -----
15253 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15258 * rt -----
15259 * rs -----
15260 * rd -----
15272 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15277 * rt -----
15278 * rs -----
15279 * rd -----
15293 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15298 * rt -----
15299 * rs -----
15300 * rd -----
15314 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15319 * rt -----
15320 * rs -----
15321 * rd -----
15333 * SYSCALL code - System Call. Cause a System Call Exception
15338 * code ------------------
15350 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15355 * rt -----
15356 * rs -----
15357 * rd -----
15372 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15377 * rt -----
15378 * rs -----
15379 * rd -----
15390 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15395 * rt -----
15396 * rs -----
15397 * rd -----
15408 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15413 * rt -----
15414 * rs -----
15415 * rd -----
15426 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15431 * rt -----
15432 * rs -----
15433 * rd -----
15444 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15449 * rt -----
15450 * rs -----
15451 * rd -----
15462 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15467 * rt -----
15468 * rs -----
15469 * rd -----
15480 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15485 * rt -----
15486 * rs -----
15487 * rd -----
15498 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15503 * rt -----
15504 * rs -----
15505 * rd -----
15516 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15521 * rt -----
15522 * rs -----
15523 * rd -----
15534 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15539 * rt -----
15540 * rs -----
15541 * rd -----
15552 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15557 * rt -----
15558 * rs -----
15559 * rd -----
15570 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15575 * rt -----
15576 * rs -----
15577 * rd -----
15588 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15593 * rt -----
15594 * rs -----
15595 * rd -----
15610 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15615 * rt -----
15616 * rs -----
15617 * rd -----
15632 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15637 * rt -----
15638 * rs -----
15639 * rd -----
15654 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15659 * rt -----
15660 * rs -----
15661 * rd -----
15676 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15681 * rt -----
15682 * rs -----
15683 * rd -----
15698 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15703 * rt -----
15704 * rs -----
15705 * rd -----
15724 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15729 * rt -----
15730 * rs -----
15731 * rd -----
15747 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15752 * rt -----
15753 * rs -----
15754 * rd -----
15773 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15778 * rt -----
15779 * rs -----
15780 * rd -----
15799 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15804 * rt -----
15805 * rs -----
15806 * rd -----
15822 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15827 * rt -----
15828 * rs -----
15829 * rd -----
15848 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15853 * rt -----
15854 * rs -----
15855 * rd -----
15867 * WAIT code - Enter Wait State
15872 * code ----------
15884 * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
15890 * rt -----
15891 * mask -------
15905 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15910 * rt -----
15911 * rs -----
15912 * rd -----
15927 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15932 * rt -----
15933 * rs -----
15934 * rd -----
15949 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15954 * rt -----
15955 * rs -----
15956 * rd -----
15973 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15978 * rt -----
15979 * rs -----
15980 * rd -----
15996 * YIELD rt, rs -
16001 * rt -----
16002 * rs -----
21866 * instruction size - negative is error
21867 * disassembly string - on error will constain error string
21892 "disassembler failure - bad table entry"); in Disassemble()
21893 return -6; in Disassemble()
21900 return -2; in Disassemble()
21906 return -1; /* failed to disassemble */ in Disassemble()
21915 if (unlikely(sigsetjmp(info->buf, 0) != 0)) { in nanomips_dis()
21924 int status = (*info->read_memory_func)(memaddr, (bfd_byte *)ret, 2, info); in read_u16()
21926 (*info->memory_error_func)(status, memaddr, info); in read_u16()
21930 if ((info->endian == BFD_ENDIAN_BIG) != HOST_BIG_ENDIAN) { in read_u16()
21942 info->bytes_per_chunk = 2; in print_insn_nanomips()
21943 info->display_endian = info->endian; in print_insn_nanomips()
21944 info->insn_info_valid = 1; in print_insn_nanomips()
21945 info->branch_delay_insns = 0; in print_insn_nanomips()
21946 info->data_size = 0; in print_insn_nanomips()
21947 info->insn_type = dis_nonbranch; in print_insn_nanomips()
21948 info->target = 0; in print_insn_nanomips()
21949 info->target2 = 0; in print_insn_nanomips()
21953 disassm_info.fprintf_func = info->fprintf_func; in print_insn_nanomips()
21954 disassm_info.stream = info->stream; in print_insn_nanomips()
21957 return -1; in print_insn_nanomips()
21961 /* Handle 32-bit opcodes. */ in print_insn_nanomips()
21964 return -1; in print_insn_nanomips()
21968 /* Handle 48-bit opcodes. */ in print_insn_nanomips()
21971 return -1; in print_insn_nanomips()
21979 (*info->fprintf_func)(info->stream, "%04x ", words[i]); in print_insn_nanomips()
21981 (*info->fprintf_func)(info->stream, " "); in print_insn_nanomips()
21986 (*info->fprintf_func) (info->stream, "%s", buf); in print_insn_nanomips()