x86/sandybridge/pipeline.json

3         "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
4         "Counter": "0,1,2,3",
12         "Counter": "0,1,2,3",
13         "CounterMask": "1",
14         "EdgeDetect": "1",
23         "Counter": "0,1,2,3",
31         "Counter": "0,1,2,3",
38         "BriefDescription": "Speculative and retired macro-conditional branches.",
39         "Counter": "0,1,2,3",
46         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
47         "Counter": "0,1,2,3",
55         "Counter": "0,1,2,3",
63         "Counter": "0,1,2,3",
71         "Counter": "0,1,2,3",
78         "BriefDescription": "Not taken macro-conditional branches.",
79         "Counter": "0,1,2,3",
86         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
87         "Counter": "0,1,2,3",
94         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
95         "Counter": "0,1,2,3",
103         "Counter": "0,1,2,3",
111         "Counter": "0,1,2,3",
119         "Counter": "0,1,2,3",
127         "Counter": "0,1,2,3",
135         "Counter": "0,1,2,3",
141         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
142         "Counter": "0,1,2,3",
150         "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
151         "Counter": "0,1,2,3",
154         "PEBS": "1",
160         "Counter": "0,1,2,3",
167         "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
168         "Counter": "0,1,2,3",
171         "PEBS": "1",
176         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
177         "Counter": "0,1,2,3",
180         "PEBS": "1",
185         "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
186         "Counter": "0,1,2,3",
189         "PEBS": "1",
194         "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
195         "Counter": "0,1,2,3",
198         "PEBS": "1",
204         "Counter": "0,1,2,3",
212         "Counter": "0,1,2,3",
220         "Counter": "0,1,2,3",
228         "Counter": "0,1,2,3",
236         "Counter": "0,1,2,3",
244         "Counter": "0,1,2,3",
247         "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
253         "Counter": "0,1,2,3",
261         "Counter": "0,1,2,3",
269         "Counter": "0,1,2,3",
277         "Counter": "0,1,2,3",
285         "Counter": "0,1,2,3",
293         "Counter": "0,1,2,3",
301         "Counter": "0,1,2,3",
307         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
308         "Counter": "0,1,2,3",
316         "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
317         "Counter": "0,1,2,3",
320         "PEBS": "1",
325         "BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
326         "Counter": "0,1,2,3",
329         "PEBS": "1",
334         "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
335         "Counter": "0,1,2,3",
338         "PEBS": "1",
343         "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
344         "Counter": "0,1,2,3",
347         "PEBS": "1",
353         "Counter": "0,1,2,3",
361         "Counter": "0,1,2,3",
368         "AnyThread": "1",
370         "Counter": "0,1,2,3",
378         "Counter": "0,1,2,3",
386         "Counter": "Fixed counter 2",
388         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
394         "Counter": "0,1,2,3",
401         "AnyThread": "1",
403         "Counter": "0,1,2,3",
411         "Counter": "Fixed counter 1",
413         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
418         "AnyThread": "1",
420         "Counter": "Fixed counter 1",
427         "Counter": "0,1,2,3",
433         "AnyThread": "1",
435         "Counter": "0,1,2,3",
441         "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
442         "Counter": "2",
450         "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
451         "Counter": "0,1,2,3",
452         "CounterMask": "1",
459         "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
460         "Counter": "0,1,2,3",
468         "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
469         "Counter": "2",
477         "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
478         "Counter": "0,1,2,3",
487         "Counter": "0,1,2,3",
495         "Counter": "0,1,2,3",
503         "Counter": "Fixed counter 0",
505         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
510         "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
511         "Counter": "0,1,2,3",
517         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
518         "Counter": "1",
527         "Counter": "0,1,2,3",
535         "Counter": "0,1,2,3",
536         "CounterMask": "1",
543         "AnyThread": "1",
545         "Counter": "0,1,2,3",
546         "CounterMask": "1",
554         "Counter": "0,1,2,3",
555         "CounterMask": "1",
556         "EdgeDetect": "1",
563         "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
564         "Counter": "0,1,2,3",
572         "Counter": "0,1,2,3",
580         "Counter": "0,1,2,3",
587         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
588         "Counter": "0,1,2,3",
591         "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store.  See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
597         "Counter": "0,1,2,3",
606         "Counter": "0,1,2,3",
613         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
614         "Counter": "0,1,2,3",
621         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
622         "Counter": "0,1,2,3",
630         "Counter": "0,1,2,3",
639         "Counter": "0,1,2,3",
640         "CounterMask": "1",
648         "Counter": "0,1,2,3",
656         "Counter": "0,1,2,3",
657         "CounterMask": "1",
658         "EdgeDetect": "1",
666         "Counter": "0,1,2,3",
669         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
674         "BriefDescription": "Self-modifying code (SMC) detected.",
675         "Counter": "0,1,2,3",
678         "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",
684         "Counter": "0,1,2,3",
691         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
692         "Counter": "0,1,2,3",
699         "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
700         "Counter": "0,1,2,3",
701         "CounterMask": "1",
704         "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.",
710         "Counter": "0,1,2,3",
718         "Counter": "0,1,2,3",
721         "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
726         "BriefDescription": "Resource-related stall cycles.",
727         "Counter": "0,1,2,3",
735         "Counter": "0,1,2,3",
743         "Counter": "0,1,2,3",
751         "Counter": "0,1,2,3",
759         "Counter": "0,1,2,3",
766         "BriefDescription": "Cycles stalled due to re-order buffer full.",
767         "Counter": "0,1,2,3",
775         "Counter": "0,1,2,3",
783         "Counter": "0,1,2,3",
791         "Counter": "0,1,2,3",
799         "Counter": "0,1,2,3",
807         "Counter": "0,1,2,3",
815         "Counter": "0,1,2,3",
823         "Counter": "0,1,2,3",
831         "Counter": "0,1,2,3",
839         "Counter": "0,1,2,3",
840         "CounterMask": "1",
841         "EdgeDetect": "1",
844         "Invert": "1",
850         "Counter": "0,1,2,3",
858         "Counter": "0,1,2,3",
866         "Counter": "0,1,2,3",
873         "AnyThread": "1",
875         "Counter": "0,1,2,3",
882         "BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
883         "Counter": "0,1,2,3",
890         "AnyThread": "1",
891         "BriefDescription": "Cycles per core when uops are dispatched to port 1.",
892         "Counter": "0,1,2,3",
900         "Counter": "0,1,2,3",
907         "AnyThread": "1",
909         "Counter": "0,1,2,3",
917         "Counter": "0,1,2,3",
924         "AnyThread": "1",
926         "Counter": "0,1,2,3",
934         "Counter": "0,1,2,3",
941         "AnyThread": "1",
943         "Counter": "0,1,2,3",
951         "Counter": "0,1,2,3",
958         "AnyThread": "1",
960         "Counter": "0,1,2,3",
967         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
968         "Counter": "0,1,2,3",
969         "CounterMask": "1",
976         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
977         "Counter": "0,1,2,3",
985         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
986         "Counter": "0,1,2,3",
994         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
995         "Counter": "0,1,2,3",
1003         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1004         "Counter": "0,1,2,3",
1007         "Invert": "1",
1013         "Counter": "0,1,2,3",
1016         "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1021         "AnyThread": "1",
1023         "Counter": "0,1,2,3",
1024         "CounterMask": "1",
1027         "Invert": "1",
1033         "Counter": "0,1,2,3",
1034         "CounterMask": "1",
1037         "Invert": "1",
1042         "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
1043         "Counter": "0,1,2,3",
1046         "PEBS": "1",
1047         "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
1053         "Counter": "0,1,2,3",
1054         "CounterMask": "1",
1057         "Invert": "1",
1062         "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
1063         "Counter": "0,1,2,3",
1066         "PEBS": "1",
1067         "PublicDescription": "This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)",
1073         "Counter": "0,1,2,3",
1074         "CounterMask": "1",
1077         "Invert": "1",
1083         "Counter": "0,1,2,3",
1087         "Invert": "1",