x86/arrowlake/cache.json

26 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
32 …: "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and …
36         "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cache.",
66 …icDescription": "Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-por…
76 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
163         "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
167 …ropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
197 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 …
206 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
221 …"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MIS…
225 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
263 …quests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses t…
273 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
313 …ublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss exc…
319 …"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.M…
323 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
333 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
343         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
353         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
369 …"BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetche…
373 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
379 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch…
383 …n": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests i…
399 …ption": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss.",
408 …ts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in t…
412 …re is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in …
418 …ts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in t…
422 …re is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in …
428 …ts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed i…
575 …"PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST c…
592         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
597 …"PublicDescription": "Counts retired load instructions that split across a cacheline boundary. Ava…
603         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
608 …"PublicDescription": "Counts retired store instructions that split across a cacheline boundary. Av…
619 …tion": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Availabl…
630 …"PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB). A…
641 …n": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Availabl…
652 …": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Availabl…
658 …ed load instructions whose data sources were a cross-core Snoop hits and forwards data from an in …
663 …ed load instructions whose data sources were a cross-core Snoop hits and forwards data from an in …
669 …d instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally exc…
674 …d instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally exc…
680 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
685 …tired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core …
691 …: "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
696 …ts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core c…
707 …instructions with at least one load to uncacheable memory-type, or at least one cache-line split l…
1031 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1043 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1055 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1067 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1079 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1091 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1103 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1115 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1127 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1139 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1151 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1163 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1175 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1187 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1199 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1211 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1223 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1235 …d that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEB…
1271         "EventName": "MEM_UOPS_RETIRED.SPLIT",
1281         "EventName": "MEM_UOPS_RETIRED.SPLIT",
1287         "BriefDescription": "Counts the number of retired split load uops.",
1297         "BriefDescription": "Counts the number of retired split load uops.",
1307         "BriefDescription": "Counts the number of retired split store uops.",
1317         "BriefDescription": "Counts the number of retired split store uops.",
1327 …BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
1337 …   "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
1347 …  "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
1381 …"PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
1467         "BriefDescription": "Cacheable and Non-Cacheable code read requests",
1471         "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.",
1502 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
1544 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
1570         "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
1574 … number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO tr…
1580         "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
1584 …ing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncach…