s390/cf_z17/extended.json

3 		"Unit": "CPU-M-CF",
6 		"BriefDescription": "L1D Read-only Exclusive Writes",
7 		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
10 		"Unit": "CPU-M-CF",
14 		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
17 		"Unit": "CPU-M-CF",
21 		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
24 		"Unit": "CPU-M-CF",
28 		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
31 		"Unit": "CPU-M-CF",
34 		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
35 		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
38 		"Unit": "CPU-M-CF",
42 		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
45 		"Unit": "CPU-M-CF",
49 		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
52 		"Unit": "CPU-M-CF",
56 		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
59 		"Unit": "CPU-M-CF",
63 		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
66 		"Unit": "CPU-M-CF",
70 		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
73 		"Unit": "CPU-M-CF",
77 		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
80 		"Unit": "CPU-M-CF",
83 		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
84 		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
87 		"Unit": "CPU-M-CF",
91 		"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-2 TLB miss is in progress."
94 		"Unit": "CPU-M-CF",
97 		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
98 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
101 		"Unit": "CPU-M-CF",
104 		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
105 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
108 		"Unit": "CPU-M-CF",
111 		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit",
112 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
115 		"Unit": "CPU-M-CF",
118 		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit",
119 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
122 		"Unit": "CPU-M-CF",
125 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache",
126 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
129 		"Unit": "CPU-M-CF",
132 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention",
133 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
136 		"Unit": "CPU-M-CF",
139 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit",
140 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
143 		"Unit": "CPU-M-CF",
146 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit",
147 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
150 		"Unit": "CPU-M-CF",
153 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Module L2-Cache",
154 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
157 		"Unit": "CPU-M-CF",
160 		"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L2-Cache",
161 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
164 		"Unit": "CPU-M-CF",
167 		"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer L2-Cache",
168 		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
171 		"Unit": "CPU-M-CF",
174 		"BriefDescription": "Directory Write Level 1 Cache from On-Chip Memory",
175 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
178 		"Unit": "CPU-M-CF",
181 		"BriefDescription": "Directory Write Level 1 Cache from On-Module Memory",
182 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
185 		"Unit": "CPU-M-CF",
188 		"BriefDescription": "Directory Write Level 1 Cache from On-Drawer Memory",
189 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
192 		"Unit": "CPU-M-CF",
195 		"BriefDescription": "Directory Write Level 1 Cache from Off-Drawer Memory",
196 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
199 		"Unit": "CPU-M-CF",
202 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention",
203 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
206 		"Unit": "CPU-M-CF",
209 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit",
210 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
213 		"Unit": "CPU-M-CF",
216 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit",
217 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
220 		"Unit": "CPU-M-CF",
223 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention",
224 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
227 		"Unit": "CPU-M-CF",
230 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit",
231 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
234 		"Unit": "CPU-M-CF",
237 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit",
238 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
241 		"Unit": "CPU-M-CF",
244 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention",
245 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
248 		"Unit": "CPU-M-CF",
251 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit",
252 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
255 		"Unit": "CPU-M-CF",
258 		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit",
259 		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
262 		"Unit": "CPU-M-CF",
265 		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache",
266 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
269 		"Unit": "CPU-M-CF",
272 		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Intervention",
273 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
276 		"Unit": "CPU-M-CF",
279 		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit",
280 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
283 		"Unit": "CPU-M-CF",
286 		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit",
287 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
290 		"Unit": "CPU-M-CF",
293 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache",
294 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
297 		"Unit": "CPU-M-CF",
300 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention",
301 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
304 		"Unit": "CPU-M-CF",
307 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit",
308 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
311 		"Unit": "CPU-M-CF",
314 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit",
315 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache after using drawer level horizontal persistence, Drawer-HP hit."
318 		"Unit": "CPU-M-CF",
321 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module L2-Cache",
322 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
325 		"Unit": "CPU-M-CF",
328 		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache",
329 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
332 		"Unit": "CPU-M-CF",
335 		"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache",
336 		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
339 		"Unit": "CPU-M-CF",
342 		"BriefDescription": "CPU is not in wait state and CPU is running by itself",
343 		"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running by itself on the Core."
346 		"Unit": "CPU-M-CF",
349 		"BriefDescription": "CPU is not in wait state and CPU is running by another thread",
350 		"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running with another thread on the Core."
353 		"Unit": "CPU-M-CF",
356 		"BriefDescription": "Instructions executed on CPU by itself",
357 		"PublicDescription": "The number of instructions executed on the CPU and the CPU is running by itself on the Core."
360 		"Unit": "CPU-M-CF",
363 		"BriefDescription": "Instructions executed on CPU by another thread",
364 		"PublicDescription": "The number of instructions executed on the CPU and the CPU is running with another thread on the Core."
367 		"Unit": "CPU-M-CF",
374 		"Unit": "CPU-M-CF",
381 		"Unit": "CPU-M-CF",
388 		"Unit": "CPU-M-CF",
395 		"Unit": "CPU-M-CF",
399 		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
402 		"Unit": "CPU-M-CF",
406 		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
409 		"Unit": "CPU-M-CF",
413 		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
416 		"Unit": "CPU-M-CF",
419 		"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
420 		"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit."
423 		"Unit": "CPU-M-CF",
426 		"BriefDescription": "Cycles CPU is using Deflate unit",
427 		"PublicDescription": "Cycles CPU is using Deflate unit."
430 		"Unit": "CPU-M-CF",
437 		"Unit": "CPU-M-CF",
444 		"Unit": "CPU-M-CF",
448 		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed that ended in Condition Codes 0, 1 or 2."
451 		"Unit": "CPU-M-CF",
458 		"Unit": "CPU-M-CF",
465 		"Unit": "CPU-M-CF",
469 		"PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
472 		"Unit": "CPU-M-CF",
476 		"PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
479 		"Unit": "CPU-M-CF",
482 		"BriefDescription": "NNPA instructions used on-chip Integrated Accelerator",
483 		"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used the Local On-Chip IBM Z Integrated Accelerator for AI during its execution"
486 		"Unit": "CPU-M-CF",
489 		"BriefDescription": "NNPA instructions used off-chip Integrated Accelerator",
490 		"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used an Off-Chip IBM Z Integrated Accelerator for AI during its execution."
493 		"Unit": "CPU-M-CF",
500 		"Unit": "CPU-M-CF",
507 		"Unit": "CPU-M-CF",
514 		"Unit": "CPU-M-CF",
518 		"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU did not use any special logic to allow the PLO to complete."
521 		"Unit": "CPU-M-CF",
525 		"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU is using special logic to allow PLO to complete."
528 		"Unit": "CPU-M-CF",
535 		"Unit": "CPU-M-CF",