soc/tegra/tegra186_asrc.c

23 #define ASRC_STREAM_SOURCE_SELECT(id)					       \
24 	(TEGRA186_ASRC_CFG + ((id) * TEGRA186_ASRC_STREAM_STRIDE))
26 #define ASRC_STREAM_REG(reg, id) ((reg) + ((id) * TEGRA186_ASRC_STREAM_STRIDE))
28 #define ASRC_STREAM_REG_DEFAULTS(id)					       \
29 	{ ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),			       \
30 	  (((id) + 1) << 4) },						       \
31 	{ ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id),		       \
33 	{ ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id),		       \
35 	{ ASRC_STREAM_REG(TEGRA186_ASRC_MUTE_UNMUTE_DURATION, id),	       \
37 	{ ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, id),		       \
39 	{ ASRC_STREAM_REG(TEGRA186_ASRC_TX_CIF_CTRL, id),		       \
70 				      unsigned int id)
74 				     id),
91 	int id;
107 	for (id = 0; id < TEGRA186_ASRC_STREAM_MAX; id++) {
108 		if (asrc->lane[id].ratio_source !=
114 					id),
115 			asrc->lane[id].int_part);
119 					id),
120 			asrc->lane[id].frac_part);
122 		tegra186_asrc_lock_stream(asrc, id);
167 	int ret, id = dai->id;
171 		     ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, dai->id),
172 		     asrc->lane[id].input_thresh);
175 		ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, dai->id));
177 		dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret);
190 	int ret, id = dai->id - 7;
194 		     ASRC_STREAM_REG(TEGRA186_ASRC_TX_THRESHOLD, id),
195 		     asrc->lane[id].output_thresh);
198 		ASRC_STREAM_REG(TEGRA186_ASRC_TX_CIF_CTRL, id));
200 		dev_err(dev, "Can't set ASRC TX%d CIF: %d\n", id, ret);
205 	if (asrc->lane[id].hwcomp_disable) {
207 			ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
212 			ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
217 			ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_COMP, id),
223 			   ASRC_STREAM_REG(TEGRA186_ASRC_CFG, id),
224 			   1, asrc->lane[id].ratio_source);
226 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) {
228 			ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id),
229 			asrc->lane[id].int_part);
231 			ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id),
232 			asrc->lane[id].frac_part);
233 		tegra186_asrc_lock_stream(asrc, id);
246 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
248 	ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source;
260 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
263 	asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];
267 				 asrc->lane[id].ratio_source,
280 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
283 		    ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, id),
284 		    &asrc->lane[id].int_part);
286 	ucontrol->value.integer.value[0] = asrc->lane[id].int_part;
298 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
301 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
304 			id);
308 	asrc->lane[id].int_part = ucontrol->value.integer.value[0];
312 						 id),
314 				 asrc->lane[id].int_part, &change);
316 	tegra186_asrc_lock_stream(asrc, id);
328 	unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE;
331 		    ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_FRAC_PART, id),
332 		    &asrc->lane[id].frac_part);
334 	ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;
346 	unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE;
349 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {
352 			id);
356 	asrc->lane[id].frac_part = ucontrol->value.integer.value[0];
360 						 id),
362 				 asrc->lane[id].frac_part, &change);
364 	tegra186_asrc_lock_stream(asrc, id);
376 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
378 	ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable;
390 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
393 	if (value == asrc->lane[id].hwcomp_disable)
396 	asrc->lane[id].hwcomp_disable = value;
408 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
410 	ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3);
422 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
423 	int value = (asrc->lane[id].input_thresh & ~(0x3)) |
426 	if (value == asrc->lane[id].input_thresh)
429 	asrc->lane[id].input_thresh = value;
441 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
443 	ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3);
455 	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
456 	int value = (asrc->lane[id].output_thresh & ~(0x3)) |
459 	if (value == asrc->lane[id].output_thresh)
462 	asrc->lane[id].output_thresh = value;
472 	unsigned int id =
476 		     ASRC_STREAM_REG(TEGRA186_ASRC_SOFT_RESET, id),
490 #define IN_DAI(id)						\
492 		.name = "ASRC-RX-CIF"#id,			\
494 			.stream_name = "RX" #id "-CIF-Playback",\
504 			.stream_name = "RX" #id "-CIF-Capture", \
516 #define OUT_DAI(id)						\
518 		.name = "ASRC-TX-CIF"#id,			\
520 			.stream_name = "TX" #id "-CIF-Playback",\
530 			.stream_name = "TX" #id "-CIF-Capture",	\
608 #define ASRC_STREAM_ROUTE(id, sname)					   \
609 	{ "RX" #id " XBAR-" sname,      NULL,   "RX" #id " XBAR-TX" },	   \
610 	{ "RX" #id "-CIF-" sname,       NULL,   "RX" #id " XBAR-" sname }, \
611 	{ "RX" #id,                     NULL,   "RX" #id "-CIF-" sname },  \
612 	{ "TX" #id,			NULL,   "RX" #id },		   \
613 	{ "TX" #id "-CIF-" sname,       NULL,   "TX" #id },		   \
614 	{ "TX" #id " XBAR-" sname,      NULL,   "TX" #id "-CIF-" sname },  \
615 	{ "TX" #id " XBAR-RX",          NULL,   "TX" #id " XBAR-" sname },
617 #define ASRC_ROUTE(id)							   \
618 	ASRC_STREAM_ROUTE(id, "Playback")				   \
619 	ASRC_STREAM_ROUTE(id, "Capture")
643 #define ASRC_SOURCE_DECL(name, id)					\
645 		SOC_ENUM_SINGLE(ASRC_STREAM_SOURCE_SELECT(id),		\