soc/stm/stm32_sai.c

22 static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai);
55 	{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
56 	{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
57 	{ .compatible = "st,stm32mp25-sai", .data = (void *)&stm32_sai_conf_mp25 },
63 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
65 	clk_disable_unprepare(sai->pclk);
72 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
75 	ret = clk_prepare_enable(sai->pclk);
77 		dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
84 static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
89 	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
93 	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
95 	stm32_sai_pclk_disable(&sai->pdev->dev);
100 static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
106 	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
110 	dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
111 		sai->pdev->dev.of_node,
114 	prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
116 		dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
117 			sai->pdev->dev.of_node,
119 		stm32_sai_pclk_disable(&sai->pdev->dev);
123 	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
125 	stm32_sai_pclk_disable(&sai->pdev->dev);
167 static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai)
169 	struct device *dev = &sai->pdev->dev;
171 	sai->clk_x8k = devm_clk_get(dev, "x8k");
172 	if (IS_ERR(sai->clk_x8k))
173 		return dev_err_probe(dev, PTR_ERR(sai->clk_x8k),
176 	sai->clk_x11k = devm_clk_get(dev, "x11k");
177 	if (IS_ERR(sai->clk_x11k))
178 		return dev_err_probe(dev, PTR_ERR(sai->clk_x11k),
186 	struct stm32_sai_data *sai;
192 	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
193 	if (!sai)
196 	sai->pdev = pdev;
198 	sai->base = devm_platform_ioremap_resource(pdev, 0);
199 	if (IS_ERR(sai->base))
200 		return PTR_ERR(sai->base);
204 		memcpy(&sai->conf, (const struct stm32_sai_conf *)conf,
209 	if (!STM_SAI_IS_F4(sai)) {
210 		sai->pclk = devm_clk_get(&pdev->dev, "pclk");
211 		if (IS_ERR(sai->pclk))
212 			return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
216 	if (sai->conf.get_sai_ck_parent) {
217 		ret = sai->conf.get_sai_ck_parent(sai);
223 	sai->irq = platform_get_irq(pdev, 0);
224 	if (sai->irq < 0)
225 		return sai->irq;
238 	ret = clk_prepare_enable(sai->pclk);
245 			readl_relaxed(sai->base + STM_SAI_IDR));
247 		val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
248 		sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
249 		sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
252 		val = readl_relaxed(sai->base + STM_SAI_VERR);
253 		sai->conf.version = val;
259 	clk_disable_unprepare(sai->pclk);
261 	sai->set_sync = &stm32_sai_set_sync;
262 	platform_set_drvdata(pdev, sai);
268  * When pins are shared by two sai sub instances, pins have to be defined
269  * in sai parent node. In this case, pins state is not managed by alsa fw.
274 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
281 	sai->gcr = readl_relaxed(sai->base);
289 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
296 	writel_relaxed(sai->gcr, sai->base);
310 		.name = "st,stm32-sai",
321 MODULE_ALIAS("platform:st,stm32-sai");