Lines Matching refs:sdev
34 static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev)
36 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
42 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
66 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
68 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
77 ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
80 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
84 hda_ssp_set_cbp_cfp(sdev);
91 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
94 ret = hda_dsp_core_run(sdev, chip->init_core_mask);
97 dev_err(sdev->dev,
104 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
113 dev_err(sdev->dev,
120 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
126 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask &
130 dev_err(sdev->dev,
136 hda_dsp_ipc_int_enable(sdev);
148 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
156 sdev->enabled_cores_mask |= chip->init_core_mask;
157 mask = sdev->enabled_cores_mask;
159 sdev->dsp_core_ref_count[j]++;
164 dev_err(sdev->dev,
177 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
178 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
187 struct snd_sof_dev *sdev = dev_get_drvdata(dev);
199 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
203 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
213 return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
227 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream)
229 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
234 dev_dbg(sdev->dev, "Code loader DMA starting\n");
236 ret = hda_cl_trigger(sdev->dev, hext_stream, SNDRV_PCM_TRIGGER_START);
238 dev_err(sdev->dev, "error: DMA trigger start failed\n");
242 dev_dbg(sdev->dev, "waiting for FW_ENTERED status\n");
244 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
256 dev_err(sdev->dev,
260 dev_dbg(sdev->dev, "Code loader FW_ENTERED status\n");
263 ret = hda_cl_trigger(sdev->dev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
265 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
269 dev_dbg(sdev->dev, "Code loader DMA stopped\n");
275 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
277 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
283 original_gb = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP) &
290 iccmax_stream = hda_cl_prepare(sdev->dev, HDA_CL_STREAM_FORMAT, PAGE_SIZE,
294 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
298 ret = hda_dsp_cl_boot_firmware(sdev);
304 ret1 = hda_cl_cleanup(sdev->dev, &hda->iccmax_dmab,
307 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
315 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
322 static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
327 chip_info = get_chip_info(sdev->pdata);
329 ret = chip_info->cl_init(sdev, 0, true);
334 hda_sdw_process_wakeen(sdev);
339 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
341 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
342 struct snd_sof_pdata *plat_data = sdev->pdata;
349 if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) {
350 dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
352 ret = hda_dsp_boot_imr(sdev);
358 dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
365 if (sdev->basefw.fw->size <= sdev->basefw.payload_offset) {
366 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
371 init_waitqueue_head(&sdev->boot_wait);
374 stripped_firmware.size = sdev->basefw.fw->size - sdev->basefw.payload_offset;
375 hext_stream = hda_cl_prepare(sdev->dev, HDA_CL_STREAM_FORMAT,
380 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
391 stripped_firmware.data = sdev->basefw.fw->data + sdev->basefw.payload_offset;
398 dev_dbg(sdev->dev,
403 ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
413 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
433 if (!sdev->first_boot)
434 hda_sdw_process_wakeen(sdev);
444 ret = hda_cl_copy_fw(sdev, hext_stream);
446 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
449 snd_sof_dsp_dbg_dump(sdev, "Firmware download failed",
460 ret1 = hda_cl_cleanup(sdev->dev, &hda->cl_dmab,
463 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
478 hda_dsp_ctrl_ppcap_enable(sdev, false);
484 int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
487 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
488 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
516 hext_stream = hda_cl_prepare(sdev->dev, HDA_CL_STREAM_FORMAT,
521 dev_err(sdev->dev, "%s: DMA prepare failed\n", __func__);
539 ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
549 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
557 dev_warn(sdev->dev,
563 ret = hda_cl_trigger(sdev->dev, hext_stream, SNDRV_PCM_TRIGGER_START);
565 dev_err(sdev->dev, "%s: DMA trigger start failed\n", __func__);
577 ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
580 ret1 = hda_cl_trigger(sdev->dev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
582 dev_err(sdev->dev, "%s: DMA trigger stop failed\n", __func__);
589 ret1 = hda_cl_cleanup(sdev->dev, &hda->cl_dmab, persistent_cl_buffer,
592 dev_err(sdev->dev, "%s: Code loader DSP cleanup failed\n", __func__);
603 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
608 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
615 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
626 dev_dbg(sdev->dev, "FW clock config: %s\n",
634 dev_info(sdev->dev, "unsupported token type: %d\n",