Lines Matching defs:afe

3  * mt8188-afe-clk.c  --  MediaTek 8188 afe clock ctrl
13 #include "mt8188-afe-common.h"
14 #include "mt8188-afe-clk.h"
51 	/* afe clock gate */
234 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
241 	regmap_update_bits(afe->regmap,
246 	regmap_update_bits(afe->regmap,
251 	regmap_update_bits(afe->regmap,
259 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
262 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
266 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
267 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
270 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
271 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
280 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
283 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
287 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
288 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
291 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
292 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
301 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
310 	ret = mt8188_afe_setup_apll_tuner(afe, id);
314 	ret = mt8188_afe_enable_tuner_clk(afe, id);
322 		regmap_update_bits(afe->regmap,
332 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
345 		regmap_update_bits(afe->regmap,
354 	ret = mt8188_afe_disable_tuner_clk(afe, id);
375 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
377 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
381 		dev_dbg(afe->dev, "invalid clk id\n");
394 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
399 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
407 int mt8188_afe_init_clock(struct mtk_base_afe *afe)
409 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
412 	ret = mt8188_audsys_clk_register(afe);
414 		dev_err(afe->dev, "register audsys clk fail %d\n", ret);
419 		devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
425 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
427 			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
438 			dev_info(afe->dev, "%s(), init apll_tuner%d failed",
447 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
454 			dev_dbg(afe->dev, "%s(), failed to enable clk\n",
459 		dev_dbg(afe->dev, "NULL clk\n");
465 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
470 		dev_dbg(afe->dev, "NULL clk\n");
474 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
482 			dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
491 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
499 			dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",
558 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
564 	regmap_update_bits(afe->regmap, reg, mask, val);
569 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
575 	regmap_update_bits(afe->regmap, reg, mask, val);
580 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
582 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
585 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
588 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
591 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
594 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
595 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
596 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
601 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
603 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
605 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
606 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
607 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
608 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
609 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
610 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
615 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
617 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
621 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
623 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
627 static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)
629 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
632 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
636 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
639 static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)
641 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
643 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
644 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
648 static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)
650 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
653 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
657 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
660 static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)
662 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
664 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
665 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
669 int mt8188_apll1_enable(struct mtk_base_afe *afe)
671 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
674 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
678 	ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
683 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
687 	ret = mt8188_afe_enable_a1sys(afe);
694 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
696 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
699 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
704 int mt8188_apll1_disable(struct mtk_base_afe *afe)
706 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
708 	mt8188_afe_disable_a1sys(afe);
709 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
710 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
712 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
717 int mt8188_apll2_enable(struct mtk_base_afe *afe)
721 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
725 	ret =  mt8188_afe_enable_a2sys(afe);
731 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
736 int mt8188_apll2_disable(struct mtk_base_afe *afe)
738 	mt8188_afe_disable_a2sys(afe);
739 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
743 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
745 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
746 	mt8188_afe_enable_afe_on(afe);
750 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
752 	mt8188_afe_disable_afe_on(afe);
753 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);