intel/boards/sof_rt5682.c

34 /* Default: MCLK on, MCLK 19.2M, SSP0  */
152 			dev_err(rtd->dev, "invalid mclk freq %d\n", mclk_freq);
156 		/* need to enable ASRC function for 24MHz mclk rate */
201 			ret = clk_prepare_enable(ctx->rt5682.mclk);
203 				clk_disable_unprepare(ctx->rt5682.mclk);
205 			ret = clk_set_rate(ctx->rt5682.mclk, 19200000);
208 				dev_err(rtd->dev, "unable to set MCLK rate\n");
264 			ret = clk_prepare_enable(ctx->rt5682.mclk);
267 					"could not configure MCLK state");
288 		/* get the tplg configured mclk. */
291 			dev_err(rtd->dev, "invalid mclk freq %d\n", pll_in);
321 	/* when MCLK is 512FS, no need to set PLL configuration additionally. */
354 				 * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1  We don't test
357 				 * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
566 		 * Currently, On SKL+ platforms MCLK will be turned off in sof
572 		 * It can be removed once we can control MCLK by driver.
714 			ctx->rt5682.mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
715 			if (IS_ERR(ctx->rt5682.mclk)) {
716 				ret = PTR_ERR(ctx->rt5682.mclk);
719 					"Failed to get MCLK from pmc_plt_clk_3: %d\n",
724 			ret = clk_prepare_enable(ctx->rt5682.mclk);
727 					"could not configure MCLK state");