soc/fsl/fsl_esai.c

45  * @fifo_depth: depth of tx/rx FIFO
50  * @channels: channel num for tx or rx
56  * @synchronous: if using tx/rx synchronous mode
160  * @tx: current setting is for playback or capture
165 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
234 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
243 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
264 	bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
272 			in ? "in" : "out", tx ? 'T' : 'R');
277 	if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
281 	esai_priv->sck_div[tx] = true;
284 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
323 				tx ? 'T' : 'R');
330 		ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
335 				tx ? 'T' : 'R');
339 	ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
343 	esai_priv->sck_div[tx] = false;
346 	esai_priv->hck_dir[tx] = dir;
347 	esai_priv->hck_rate[tx] = freq;
350 			   tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
359  * @tx: direction boolean
362 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
365 	u32 hck_rate = esai_priv->hck_rate[tx];
370 	if (esai_priv->consumer_mode || esai_priv->sck_rate[tx] == freq)
383 				tx ? 'T' : 'R');
388 	if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
393 	ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
394 			esai_priv->sck_div[tx] ? 0 : ratio);
399 	esai_priv->sck_rate[tx] = freq;
540 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
554 	ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
561 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
563 	if (!tx && esai_priv->synchronous)
567 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
571 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
575 	      (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
577 	     (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
579 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
581 	if (tx)
649 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
651 	u8 i, channels = esai_priv->channels[tx];
655 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
659 	for (i = 0; tx && i < channels; i++)
674 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
675 			   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
676 			   tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
677 	mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
679 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
681 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
685 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
689 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
691 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
694 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
695 			   tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
696 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
698 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
702 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
704 	regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
711 	bool tx = true, rx = false, enabled[2];
719 	enabled[tx] = tfcr & ESAI_xFCR_xFEN;
722 	/* Stop the tx & rx */
723 	fsl_esai_trigger_stop(esai_priv, tx);
748 	/* Restart tx / rx, if they already enabled */
749 	if (enabled[tx])
750 		fsl_esai_trigger_start(esai_priv, tx);
761 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
764 	esai_priv->channels[tx] = substream->runtime->channels;
771 		fsl_esai_trigger_start(esai_priv, tx);
778 		fsl_esai_trigger_stop(esai_priv, tx);