soc/codecs/wm8995.c

385 	struct snd_soc_component *component;
485 static void wm8995_update_class_w(struct snd_soc_component *component)
492 	reg = snd_soc_component_read(component, WM8995_DAC1_LEFT_MIXER_ROUTING);
495 		dev_dbg(component->dev, "Class W source AIF2DAC\n");
499 		dev_dbg(component->dev, "Class W source AIF1DAC2\n");
503 		dev_dbg(component->dev, "Class W source AIF1DAC1\n");
507 		dev_dbg(component->dev, "DAC mixer setting: %x\n", reg);
512 	reg_r = snd_soc_component_read(component, WM8995_DAC1_RIGHT_MIXER_ROUTING);
514 		dev_dbg(component->dev, "Left and right DAC mixers different\n");
519 		dev_dbg(component->dev, "Class W enabled\n");
520 		snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
525 		dev_dbg(component->dev, "Class W disabled\n");
526 		snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
534 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
538 	reg = snd_soc_component_read(component, WM8995_CLOCKING_1);
550 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
554 	wm8995_update_class_w(component);
561 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
566 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
573 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
580 		snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
588 static void dc_servo_cmd(struct snd_soc_component *component,
593 	dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
596 	snd_soc_component_write(component, reg, val);
599 		val = snd_soc_component_read(component, WM8995_DC_SERVO_READBACK_0);
604 	dev_err(component->dev, "Timed out waiting for DC Servo\n");
610 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
613 	reg = snd_soc_component_read(component, WM8995_ANALOGUE_HP_1);
617 		snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
622 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
630 		snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
632 		snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
635 		dc_servo_cmd(component, WM8995_DC_SERVO_2,
643 		snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
647 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
653 		snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
657 		snd_soc_component_write(component, WM8995_DC_SERVO_1, 0);
659 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
669 static int configure_aif_clock(struct snd_soc_component *component, int aif)
676 	wm8995 = snd_soc_component_get_drvdata(component);
707 		dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
713 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset,
719 static int configure_clock(struct snd_soc_component *component)
721 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
725 	wm8995 = snd_soc_component_get_drvdata(component);
728 	configure_aif_clock(component, 0);
729 	configure_aif_clock(component, 1);
747 	change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1,
760 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
764 		return configure_clock(component);
767 		configure_clock(component);
1422 	struct snd_soc_component *component = dai->component;
1436 	snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
1443 	struct snd_soc_component *component;
1447 	component = dai->component;
1520 	snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1,
1524 	snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE,
1547 	struct snd_soc_component *component;
1558 	component = dai->component;
1559 	wm8995 = snd_soc_component_get_drvdata(component);
1571 			dev_dbg(component->dev, "AIF1 using split LRCLK\n");
1583 			dev_dbg(component->dev, "AIF2 using split LRCLK\n");
1669 	snd_soc_component_update_bits(component, aif1_reg,
1671 	snd_soc_component_update_bits(component, bclk_reg,
1673 	snd_soc_component_update_bits(component, lrclk_reg,
1675 	snd_soc_component_update_bits(component, rate_reg,
1683 	struct snd_soc_component *component = codec_dai->component;
1708 	return snd_soc_component_update_bits(component, reg, mask, val);
1798 	struct snd_soc_component *component;
1804 	component = dai->component;
1805 	wm8995 = snd_soc_component_get_drvdata(component);
1807 	aif1 = snd_soc_component_read(component, WM8995_AIF1_CLOCKING_1)
1810 	aif2 = snd_soc_component_read(component, WM8995_AIF2_CLOCKING_1)
1859 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1861 	snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1865 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1870 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
1874 	snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1876 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
1880 	snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
1887 		snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1895 	snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1897 	snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1900 	configure_clock(component);
1908 	struct snd_soc_component *component;
1911 	component = dai->component;
1912 	wm8995 = snd_soc_component_get_drvdata(component);
1950 	configure_clock(component);
1955 static int wm8995_set_bias_level(struct snd_soc_component *component,
1961 	wm8995 = snd_soc_component_get_drvdata(component);
1967 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1975 				dev_err(component->dev,
1980 			snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1985 		snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1995 static int wm8995_probe(struct snd_soc_component *component)
2001 	wm8995 = snd_soc_component_get_drvdata(component);
2002 	wm8995->component = component;
2007 	ret = devm_regulator_bulk_get(component->dev,
2011 		dev_err(component->dev, "Failed to request supplies: %d\n", ret);
2030 			dev_err(component->dev,
2039 		dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
2043 	ret = snd_soc_component_read(component, WM8995_SOFTWARE_RESET);
2045 		dev_err(component->dev, "Failed to read device ID: %d\n", ret);
2050 		dev_err(component->dev, "Invalid device ID: %#x\n", ret);
2055 	ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0);
2057 		dev_err(component->dev, "Failed to issue reset: %d\n", ret);
2062 	snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME,
2064 	snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME,
2066 	snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME,
2068 	snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME,
2070 	snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME,
2072 	snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME,
2074 	snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME,
2076 	snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME,
2078 	snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
2081 	wm8995_update_class_w(component);