Lines Matching full:x1
133 #define RT5660_L_MUTE (0x1 << 15)
135 #define RT5660_VOL_L_MUTE (0x1 << 14)
137 #define RT5660_R_MUTE (0x1 << 7)
139 #define RT5660_VOL_R_MUTE (0x1 << 6)
147 #define RT5660_IN_DF1 (0x1 << 15)
151 #define RT5660_IN_DF2 (0x1 << 7)
157 #define RT5660_IN_DF3 (0x1 << 15)
161 #define RT5660_IN_DF4 (0x1 << 7)
185 #define RT5660_M_ADC_L1 (0x1 << 14)
187 #define RT5660_M_ADC_L2 (0x1 << 13)
189 #define RT5660_M_ADC_R1 (0x1 << 6)
191 #define RT5660_M_ADC_R2 (0x1 << 5)
195 #define RT5660_M_ADCMIX_L (0x1 << 15)
197 #define RT5660_M_DAC1_L (0x1 << 14)
199 #define RT5660_M_ADCMIX_R (0x1 << 7)
201 #define RT5660_M_DAC1_R (0x1 << 6)
205 #define RT5660_M_DAC_L1 (0x1 << 14)
207 #define RT5660_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
209 #define RT5660_M_DAC_R1_STO_L (0x1 << 9)
211 #define RT5660_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
213 #define RT5660_M_DAC_R1 (0x1 << 6)
215 #define RT5660_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
217 #define RT5660_M_DAC_L1_STO_R (0x1 << 1)
219 #define RT5660_DAC_L1_STO_R_VOL_MASK (0x1)
239 #define RT5660_M_BST3_RM_L (0x1 << 3)
241 #define RT5660_M_BST2_RM_L (0x1 << 2)
243 #define RT5660_M_BST1_RM_L (0x1 << 1)
245 #define RT5660_M_OM_L_RM_L (0x1)
259 #define RT5660_M_BST3_RM_R (0x1 << 3)
261 #define RT5660_M_BST2_RM_R (0x1 << 2)
263 #define RT5660_M_BST1_RM_R (0x1 << 1)
265 #define RT5660_M_OM_R_RM_R (0x1)
269 #define RT5660_M_DAC1_LM (0x1 << 14)
271 #define RT5660_M_LOVOL_M (0x1 << 13)
285 #define RT5660_M_DACR_SM (0x1 << 5)
287 #define RT5660_M_BST1_SM (0x1 << 4)
289 #define RT5660_M_BST3_SM (0x1 << 3)
291 #define RT5660_M_DACL_SM (0x1 << 2)
293 #define RT5660_M_OM_L_SM (0x1 << 1)
297 #define RT5660_M_DAC_R_SPM (0x1 << 14)
299 #define RT5660_M_DAC_L_SPM (0x1 << 13)
301 #define RT5660_M_SV_SPM (0x1 << 12)
303 #define RT5660_M_BST1_SPM (0x1 << 11)
323 #define RT5660_M_BST3_OM_L (0x1 << 5)
325 #define RT5660_M_BST2_OM_L (0x1 << 4)
327 #define RT5660_M_BST1_OM_L (0x1 << 3)
329 #define RT5660_M_RM_L_OM_L (0x1 << 2)
331 #define RT5660_M_DAC_R_OM_L (0x1 << 1)
333 #define RT5660_M_DAC_L_OM_L (0x1)
351 #define RT5660_M_BST2_OM_R (0x1 << 4)
353 #define RT5660_M_BST1_OM_R (0x1 << 3)
355 #define RT5660_M_RM_R_OM_R (0x1 << 2)
357 #define RT5660_M_DAC_L_OM_R (0x1 << 1)
359 #define RT5660_M_DAC_R_OM_R (0x1)
363 #define RT5660_PWR_I2S1 (0x1 << 15)
365 #define RT5660_PWR_DAC_L1 (0x1 << 12)
367 #define RT5660_PWR_DAC_R1 (0x1 << 11)
369 #define RT5660_PWR_ADC_L (0x1 << 2)
371 #define RT5660_PWR_ADC_R (0x1 << 1)
373 #define RT5660_PWR_CLS_D (0x1)
377 #define RT5660_PWR_ADC_S1F (0x1 << 15)
379 #define RT5660_PWR_DAC_S1F (0x1 << 11)
383 #define RT5660_PWR_VREF1 (0x1 << 15)
385 #define RT5660_PWR_FV1 (0x1 << 14)
387 #define RT5660_PWR_MB (0x1 << 13)
389 #define RT5660_PWR_BG (0x1 << 11)
391 #define RT5660_PWR_HP_L (0x1 << 7)
393 #define RT5660_PWR_HP_R (0x1 << 6)
395 #define RT5660_PWR_HA (0x1 << 5)
397 #define RT5660_PWR_VREF2 (0x1 << 4)
399 #define RT5660_PWR_FV2 (0x1 << 3)
401 #define RT5660_PWR_LDO2 (0x1 << 2)
405 #define RT5660_PWR_BST1 (0x1 << 15)
407 #define RT5660_PWR_BST2 (0x1 << 14)
409 #define RT5660_PWR_BST3 (0x1 << 13)
411 #define RT5660_PWR_MB1 (0x1 << 11)
413 #define RT5660_PWR_MB2 (0x1 << 10)
415 #define RT5660_PWR_PLL (0x1 << 9)
419 #define RT5660_PWR_OM_L (0x1 << 15)
421 #define RT5660_PWR_OM_R (0x1 << 14)
423 #define RT5660_PWR_SM (0x1 << 13)
425 #define RT5660_PWR_RM_L (0x1 << 11)
427 #define RT5660_PWR_RM_R (0x1 << 10)
431 #define RT5660_PWR_SV (0x1 << 15)
433 #define RT5660_PWR_LV_L (0x1 << 11)
435 #define RT5660_PWR_LV_R (0x1 << 10)
439 #define RT5660_I2S_MS_MASK (0x1 << 15)
442 #define RT5660_I2S_MS_S (0x1 << 15)
446 #define RT5660_I2S_O_CP_U_LAW (0x1 << 10)
451 #define RT5660_I2S_I_CP_U_LAW (0x1 << 8)
453 #define RT5660_I2S_BP_MASK (0x1 << 7)
456 #define RT5660_I2S_BP_INV (0x1 << 7)
460 #define RT5660_I2S_DL_20 (0x1 << 2)
466 #define RT5660_I2S_DF_LEFT (0x1)
471 #define RT5660_I2S_BCLK_MS1_MASK (0x1 << 15)
474 #define RT5660_I2S_BCLK_MS1_64 (0x1 << 15)
478 #define RT5660_I2S_PD1_2 (0x1 << 12)
488 #define RT5660_DAC_OSR_64 (0x1 << 2)
494 #define RT5660_ADC_OSR_64 (0x1)
499 #define RT5660_RESET_ADF (0x1 << 13)
501 #define RT5660_RESET_DAF (0x1 << 12)
503 #define RT5660_DAHPF_EN (0x1 << 11)
505 #define RT5660_ADHPF_EN (0x1 << 10)
509 #define RT5660_DMIC_1_EN_MASK (0x1 << 15)
512 #define RT5660_DMIC_1_EN (0x1 << 15)
513 #define RT5660_DMIC_1L_LH_MASK (0x1 << 13)
516 #define RT5660_DMIC_1L_LH_FALLING (0x1 << 13)
517 #define RT5660_DMIC_1R_LH_MASK (0x1 << 12)
520 #define RT5660_DMIC_1R_LH_FALLING (0x1 << 12)
521 #define RT5660_SEL_DMIC_DATA_MASK (0x1 << 11)
524 #define RT5660_SEL_DMIC_DATA_IN1P (0x1 << 11)
532 #define RT5660_SCLK_SRC_PLL1 (0x1 << 14)
537 #define RT5660_PLL1_SRC_BCLK1 (0x1 << 12)
539 #define RT5660_PLL1_PD_MASK (0x1 << 3)
542 #define RT5660_PLL1_PD_2 (0x1 << 3)
558 #define RT5660_PLL_M_BP (0x1 << 11)
562 #define RT5660_CLSD_OC_MASK (0x1 << 9)
565 #define RT5660_CLSD_OC_PD (0x1 << 9)
566 #define RT5660_AUTO_PD_MASK (0x1 << 8)
569 #define RT5660_AUTO_PD_EN (0x1 << 8)
578 #define RT5660_LOUT_CO_MASK (0x1 << 4)
581 #define RT5660_LOUT_CO_EN (0x1 << 4)
582 #define RT5660_LOUT_CB_MASK (0x1)
585 #define RT5660_LOUT_CB_PU (0x1)
588 #define RT5660_SPKVDD_DET_MASK (0x1 << 15)
591 #define RT5660_SPKVDD_DET_EN (0x1 << 15)
592 #define RT5660_SPK_AG_MASK (0x1 << 14)
595 #define RT5660_SPK_AG_EN (0x1 << 14)
598 #define RT5660_MIC1_BS_MASK (0x1 << 15)
601 #define RT5660_MIC1_BS_75AV (0x1 << 15)
602 #define RT5660_MIC2_BS_MASK (0x1 << 14)
605 #define RT5660_MIC2_BS_75AV (0x1 << 14)
606 #define RT5660_MIC1_OVCD_MASK (0x1 << 11)
609 #define RT5660_MIC1_OVCD_EN (0x1 << 11)
613 #define RT5660_MIC1_OVTH_1500UA (0x1 << 9)
615 #define RT5660_MIC2_OVCD_MASK (0x1 << 8)
618 #define RT5660_MIC2_OVCD_EN (0x1 << 8)
622 #define RT5660_MIC2_OVTH_1500UA (0x1 << 6)
624 #define RT5660_PWR_CLK25M_MASK (0x1 << 4)
627 #define RT5660_PWR_CLK25M_PU (0x1 << 4)
630 #define RT5660_EQ_SRC_MASK (0x1 << 15)
633 #define RT5660_EQ_SRC_ADC (0x1 << 15)
634 #define RT5660_EQ_UPD (0x1 << 14)
641 #define RT5660_JD_GPIO1 (0x1 << 14)
643 #define RT5660_JD_LOUT_MASK (0x1 << 11)
646 #define RT5660_JD_LOUT_EN (0x1 << 11)
647 #define RT5660_JD_LOUT_TRG_MASK (0x1 << 10)
650 #define RT5660_JD_LOUT_TRG_HI (0x1 << 10)
651 #define RT5660_JD_SPO_MASK (0x1 << 9)
654 #define RT5660_JD_SPO_EN (0x1 << 9)
655 #define RT5660_JD_SPO_TRG_MASK (0x1 << 8)
658 #define RT5660_JD_SPO_TRG_HI (0x1 << 8)
661 #define RT5660_IRQ_JD_MASK (0x1 << 15)
664 #define RT5660_IRQ_JD_NOR (0x1 << 15)
665 #define RT5660_IRQ_OT_MASK (0x1 << 14)
668 #define RT5660_IRQ_OT_NOR (0x1 << 14)
669 #define RT5660_JD_STKY_MASK (0x1 << 13)
672 #define RT5660_JD_STKY_EN (0x1 << 13)
673 #define RT5660_OT_STKY_MASK (0x1 << 12)
676 #define RT5660_OT_STKY_EN (0x1 << 12)
677 #define RT5660_JD_P_MASK (0x1 << 11)
680 #define RT5660_JD_P_INV (0x1 << 11)
681 #define RT5660_OT_P_MASK (0x1 << 10)
684 #define RT5660_OT_P_INV (0x1 << 10)
687 #define RT5660_IRQ_MB1_OC_MASK (0x1 << 15)
690 #define RT5660_IRQ_MB1_OC_NOR (0x1 << 15)
691 #define RT5660_IRQ_MB2_OC_MASK (0x1 << 14)
694 #define RT5660_IRQ_MB2_OC_NOR (0x1 << 14)
695 #define RT5660_MB1_OC_STKY_MASK (0x1 << 11)
698 #define RT5660_MB1_OC_STKY_EN (0x1 << 11)
699 #define RT5660_MB2_OC_STKY_MASK (0x1 << 10)
702 #define RT5660_MB2_OC_STKY_EN (0x1 << 10)
703 #define RT5660_MB1_OC_P_MASK (0x1 << 7)
706 #define RT5660_MB1_OC_P_INV (0x1 << 7)
707 #define RT5660_MB2_OC_P_MASK (0x1 << 6)
710 #define RT5660_MB2_OC_P_INV (0x1 << 6)
711 #define RT5660_MB1_OC_CLR (0x1 << 3)
713 #define RT5660_MB2_OC_CLR (0x1 << 2)
717 #define RT5660_GP2_PIN_MASK (0x1 << 14)
720 #define RT5660_GP2_PIN_DMIC1_SDA (0x1 << 14)
724 #define RT5660_GP1_PIN_DMIC1_SCL (0x1 << 12)
726 #define RT5660_GPIO_M_MASK (0x1 << 9)
729 #define RT5660_GPIO_M_PH (0x1 << 9)
732 #define RT5660_GP2_PF_MASK (0x1 << 5)
735 #define RT5660_GP2_PF_OUT (0x1 << 5)
736 #define RT5660_GP2_OUT_MASK (0x1 << 4)
739 #define RT5660_GP2_OUT_HI (0x1 << 4)
740 #define RT5660_GP2_P_MASK (0x1 << 3)
743 #define RT5660_GP2_P_INV (0x1 << 3)
744 #define RT5660_GP1_PF_MASK (0x1 << 2)
747 #define RT5660_GP1_PF_OUT (0x1 << 2)
748 #define RT5660_GP1_OUT_MASK (0x1 << 1)
751 #define RT5660_GP1_OUT_HI (0x1 << 1)
752 #define RT5660_GP1_P_MASK (0x1)
755 #define RT5660_GP1_P_INV (0x1)
758 #define RT5660_SV_MASK (0x1 << 15)
761 #define RT5660_SV_EN (0x1 << 15)
762 #define RT5660_SPO_SV_MASK (0x1 << 14)
765 #define RT5660_SPO_SV_EN (0x1 << 14)
766 #define RT5660_OUT_SV_MASK (0x1 << 12)
769 #define RT5660_OUT_SV_EN (0x1 << 12)
770 #define RT5660_ZCD_DIG_MASK (0x1 << 11)
773 #define RT5660_ZCD_DIG_EN (0x1 << 11)
774 #define RT5660_ZCD_MASK (0x1 << 10)
777 #define RT5660_ZCD_PU (0x1 << 10)
782 #define RT5660_ZCD_SPO_MASK (0x1 << 15)
785 #define RT5660_ZCD_SPO_EN (0x1 << 15)
786 #define RT5660_ZCD_OMR_MASK (0x1 << 8)
789 #define RT5660_ZCD_OMR_EN (0x1 << 8)
790 #define RT5660_ZCD_OML_MASK (0x1 << 7)
793 #define RT5660_ZCD_OML_EN (0x1 << 7)
794 #define RT5660_ZCD_SPM_MASK (0x1 << 6)
797 #define RT5660_ZCD_SPM_EN (0x1 << 6)
798 #define RT5660_ZCD_RMR_MASK (0x1 << 5)
801 #define RT5660_ZCD_RMR_EN (0x1 << 5)
802 #define RT5660_ZCD_RML_MASK (0x1 << 4)
805 #define RT5660_ZCD_RML_EN (0x1 << 4)
808 #define RT5660_PWR_VREF_HP (0x1 << 11)
810 #define RT5660_AUTO_DIS_AMP (0x1 << 6)
811 #define RT5660_MCLK_DET (0x1 << 5)
812 #define RT5660_POW_CLKDET (0x1 << 1)
813 #define RT5660_DIG_GATE_CTRL (0x1)