Lines Matching full:x1

539 #define RT5659_L_MUTE				(0x1 << 15)
541 #define RT5659_VOL_L_MUTE (0x1 << 14)
543 #define RT5659_R_MUTE (0x1 << 7)
545 #define RT5659_VOL_R_MUTE (0x1 << 6)
559 #define RT5659_IN1_DF_MASK (0x1 << 15)
567 #define RT5659_IN3_DF_MASK (0x1 << 15)
571 #define RT5659_IN4_DF_MASK (0x1 << 7)
583 #define RT5659_EMB_JD_EN (0x1 << 15)
585 #define RT5659_JD_MODE (0x1 << 13)
587 #define RT5659_EXT_JD_EN (0x1 << 11)
589 #define RT5659_EXT_JD_DIG (0x1 << 9)
595 #define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
603 #define RT5659_SIL_DET_MASK (0x1 << 15)
605 #define RT5659_SIL_DET_EN (0x1 << 15)
610 #define RT5659_ST_EN (0x1 << 6)
626 #define RT5659_M_DAC2_L_VOL (0x1 << 13)
628 #define RT5659_M_DAC2_R_VOL (0x1 << 12)
666 #define RT5659_M_STO1_ADC_L1 (0x1 << 15)
668 #define RT5659_M_STO1_ADC_L2 (0x1 << 14)
670 #define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)
672 #define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)
674 #define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)
676 #define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)
678 #define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)
680 #define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)
682 #define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
684 #define RT5659_M_STO1_ADC_R1 (0x1 << 6)
686 #define RT5659_M_STO1_ADC_R2 (0x1 << 5)
690 #define RT5659_M_MONO_ADC_L1 (0x1 << 15)
692 #define RT5659_M_MONO_ADC_L2 (0x1 << 14)
694 #define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)
696 #define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)
700 #define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)
702 #define RT5659_M_MONO_ADC_R1 (0x1 << 7)
704 #define RT5659_M_MONO_ADC_R2 (0x1 << 6)
706 #define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)
708 #define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)
710 #define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)
714 #define RT5659_MONO_DMIC_R_SRC_MASK 0x1
718 #define RT5659_M_ADCMIX_L (0x1 << 15)
720 #define RT5659_M_DAC1_L (0x1 << 14)
725 #define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)
730 #define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)
732 #define RT5659_M_ADCMIX_R (0x1 << 7)
734 #define RT5659_M_DAC1_R (0x1 << 6)
738 #define RT5659_M_DAC_L1_STO_L (0x1 << 15)
740 #define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)
742 #define RT5659_M_DAC_R1_STO_L (0x1 << 13)
744 #define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)
746 #define RT5659_M_DAC_L2_STO_L (0x1 << 11)
748 #define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)
750 #define RT5659_M_DAC_R2_STO_L (0x1 << 9)
752 #define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)
754 #define RT5659_M_DAC_L1_STO_R (0x1 << 7)
756 #define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)
758 #define RT5659_M_DAC_R1_STO_R (0x1 << 5)
760 #define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)
762 #define RT5659_M_DAC_L2_STO_R (0x1 << 3)
764 #define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)
766 #define RT5659_M_DAC_R2_STO_R (0x1 << 1)
768 #define RT5659_G_DAC_R2_STO_R_MASK (0x1)
772 #define RT5659_M_DAC_L1_MONO_L (0x1 << 15)
774 #define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)
776 #define RT5659_M_DAC_R1_MONO_L (0x1 << 13)
778 #define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)
780 #define RT5659_M_DAC_L2_MONO_L (0x1 << 11)
782 #define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)
784 #define RT5659_M_DAC_R2_MONO_L (0x1 << 9)
786 #define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)
788 #define RT5659_M_DAC_L1_MONO_R (0x1 << 7)
790 #define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)
792 #define RT5659_M_DAC_R1_MONO_R (0x1 << 5)
794 #define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)
796 #define RT5659_M_DAC_L2_MONO_R (0x1 << 3)
798 #define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)
800 #define RT5659_M_DAC_R2_MONO_R (0x1 << 1)
802 #define RT5659_G_DAC_R2_MONO_R_MASK (0x1)
806 #define RT5659_M_DAC_MIX_L (0x1 << 7)
808 #define RT5659_DAC_MIX_L_MASK (0x1 << 6)
810 #define RT5659_M_DAC_MIX_R (0x1 << 5)
812 #define RT5659_DAC_MIX_R_MASK (0x1 << 4)
816 #define RT5659_A_DACL1_SEL (0x1 << 3)
818 #define RT5659_A_DACR1_SEL (0x1 << 2)
820 #define RT5659_A_DACL2_SEL (0x1 << 1)
822 #define RT5659_A_DACR2_SEL (0x1 << 0)
842 #define RT5659_PDM1_L_MASK (0x1 << 15)
844 #define RT5659_M_PDM1_L (0x1 << 14)
846 #define RT5659_PDM1_R_MASK (0x1 << 13)
848 #define RT5659_M_PDM1_R (0x1 << 12)
850 #define RT5659_PDM2_BUSY (0x1 << 7)
851 #define RT5659_PDM1_BUSY (0x1 << 6)
852 #define RT5659_PDM_PATTERN (0x1 << 5)
853 #define RT5659_PDM_GAIN (0x1 << 4)
861 #define RT5659_M_BST1_RM1_L (0x1 << 5)
863 #define RT5659_M_BST2_RM1_L (0x1 << 4)
865 #define RT5659_M_BST3_RM1_L (0x1 << 3)
867 #define RT5659_M_BST4_RM1_L (0x1 << 2)
869 #define RT5659_M_INL_RM1_L (0x1 << 1)
871 #define RT5659_M_SPKVOLL_RM1_L (0x1)
875 #define RT5659_M_BST1_RM1_R (0x1 << 5)
877 #define RT5659_M_BST2_RM1_R (0x1 << 4)
879 #define RT5659_M_BST3_RM1_R (0x1 << 3)
881 #define RT5659_M_BST4_RM1_R (0x1 << 2)
883 #define RT5659_M_INR_RM1_R (0x1 << 1)
885 #define RT5659_M_HPOVOLR_RM1_R (0x1)
889 #define RT5659_M_BST3_SM_L (0x1 << 4)
891 #define RT5659_M_IN_R_SM_L (0x1 << 3)
893 #define RT5659_M_IN_L_SM_L (0x1 << 2)
895 #define RT5659_M_BST1_SM_L (0x1 << 1)
897 #define RT5659_M_DAC_L2_SM_L (0x1)
901 #define RT5659_M_BST3_SM_R (0x1 << 4)
903 #define RT5659_M_IN_R_SM_R (0x1 << 3)
905 #define RT5659_M_IN_L_SM_R (0x1 << 2)
907 #define RT5659_M_BST4_SM_R (0x1 << 1)
909 #define RT5659_M_DAC_R2_SM_R (0x1)
913 #define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)
915 #define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)
917 #define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)
919 #define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)
923 #define RT5659_M_MONOVOL_MA (0x1 << 9)
925 #define RT5659_M_DAC_L2_MA (0x1 << 8)
927 #define RT5659_M_BST3_MM (0x1 << 4)
929 #define RT5659_M_BST2_MM (0x1 << 3)
931 #define RT5659_M_BST1_MM (0x1 << 2)
933 #define RT5659_M_DAC_R2_MM (0x1 << 1)
935 #define RT5659_M_DAC_L2_MM (0x1)
951 #define RT5659_M_BST3_OM_L (0x1 << 4)
953 #define RT5659_M_BST2_OM_L (0x1 << 3)
955 #define RT5659_M_BST1_OM_L (0x1 << 2)
957 #define RT5659_M_IN_L_OM_L (0x1 << 1)
959 #define RT5659_M_DAC_L2_OM_L (0x1)
963 #define RT5659_M_BST4_OM_R (0x1 << 4)
965 #define RT5659_M_BST3_OM_R (0x1 << 3)
967 #define RT5659_M_BST2_OM_R (0x1 << 2)
969 #define RT5659_M_IN_R_OM_R (0x1 << 1)
971 #define RT5659_M_DAC_R2_OM_R (0x1)
975 #define RT5659_M_DAC_L2_LM (0x1 << 15)
977 #define RT5659_M_DAC_R2_LM (0x1 << 14)
979 #define RT5659_M_OV_L_LM (0x1 << 13)
981 #define RT5659_M_OV_R_LM (0x1 << 12)
985 #define RT5659_PWR_I2S1 (0x1 << 15)
987 #define RT5659_PWR_I2S2 (0x1 << 14)
989 #define RT5659_PWR_I2S3 (0x1 << 13)
991 #define RT5659_PWR_SPDIF (0x1 << 12)
993 #define RT5659_PWR_DAC_L1 (0x1 << 11)
995 #define RT5659_PWR_DAC_R1 (0x1 << 10)
997 #define RT5659_PWR_DAC_L2 (0x1 << 9)
999 #define RT5659_PWR_DAC_R2 (0x1 << 8)
1001 #define RT5659_PWR_LDO (0x1 << 7)
1003 #define RT5659_PWR_ADC_L1 (0x1 << 4)
1005 #define RT5659_PWR_ADC_R1 (0x1 << 3)
1007 #define RT5659_PWR_ADC_L2 (0x1 << 2)
1009 #define RT5659_PWR_ADC_R2 (0x1 << 1)
1011 #define RT5659_PWR_CLS_D (0x1)
1015 #define RT5659_PWR_ADC_S1F (0x1 << 15)
1017 #define RT5659_PWR_ADC_S2F (0x1 << 14)
1019 #define RT5659_PWR_ADC_MF_L (0x1 << 13)
1021 #define RT5659_PWR_ADC_MF_R (0x1 << 12)
1023 #define RT5659_PWR_DAC_S1F (0x1 << 10)
1025 #define RT5659_PWR_DAC_MF_L (0x1 << 9)
1027 #define RT5659_PWR_DAC_MF_R (0x1 << 8)
1029 #define RT5659_PWR_PDM1 (0x1 << 7)
1033 #define RT5659_PWR_VREF1 (0x1 << 15)
1035 #define RT5659_PWR_FV1 (0x1 << 14)
1037 #define RT5659_PWR_VREF2 (0x1 << 13)
1039 #define RT5659_PWR_FV2 (0x1 << 12)
1041 #define RT5659_PWR_VREF3 (0x1 << 11)
1043 #define RT5659_PWR_FV3 (0x1 << 10)
1045 #define RT5659_PWR_MB (0x1 << 9)
1047 #define RT5659_PWR_LM (0x1 << 8)
1049 #define RT5659_PWR_BG (0x1 << 7)
1051 #define RT5659_PWR_MA (0x1 << 6)
1053 #define RT5659_PWR_HA_L (0x1 << 5)
1055 #define RT5659_PWR_HA_R (0x1 << 4)
1059 #define RT5659_PWR_BST1 (0x1 << 15)
1061 #define RT5659_PWR_BST2 (0x1 << 14)
1063 #define RT5659_PWR_BST3 (0x1 << 13)
1065 #define RT5659_PWR_BST4 (0x1 << 12)
1067 #define RT5659_PWR_MB1 (0x1 << 11)
1069 #define RT5659_PWR_MB2 (0x1 << 10)
1071 #define RT5659_PWR_MB3 (0x1 << 9)
1073 #define RT5659_PWR_BST1_P (0x1 << 6)
1075 #define RT5659_PWR_BST2_P (0x1 << 5)
1077 #define RT5659_PWR_BST3_P (0x1 << 4)
1079 #define RT5659_PWR_BST4_P (0x1 << 3)
1081 #define RT5659_PWR_JD1 (0x1 << 2)
1083 #define RT5659_PWR_JD2 (0x1 << 1)
1085 #define RT5659_PWR_JD3 (0x1)
1089 #define RT5659_PWR_BST_L (0x1 << 8)
1091 #define RT5659_PWR_BST_R (0x1 << 7)
1093 #define RT5659_PWR_PLL (0x1 << 6)
1095 #define RT5659_PWR_LDO5 (0x1 << 5)
1097 #define RT5659_PWR_LDO4 (0x1 << 4)
1099 #define RT5659_PWR_LDO3 (0x1 << 3)
1101 #define RT5659_PWR_LDO2 (0x1 << 2)
1103 #define RT5659_PWR_SVD (0x1 << 1)
1107 #define RT5659_PWR_OM_L (0x1 << 15)
1109 #define RT5659_PWR_OM_R (0x1 << 14)
1111 #define RT5659_PWR_SM_L (0x1 << 13)
1113 #define RT5659_PWR_SM_R (0x1 << 12)
1115 #define RT5659_PWR_RM1_L (0x1 << 11)
1117 #define RT5659_PWR_RM1_R (0x1 << 10)
1119 #define RT5659_PWR_MM (0x1 << 8)
1121 #define RT5659_PWR_RM2_L (0x1 << 3)
1123 #define RT5659_PWR_RM2_R (0x1 << 2)
1127 #define RT5659_PWR_SV_L (0x1 << 15)
1129 #define RT5659_PWR_SV_R (0x1 << 14)
1131 #define RT5659_PWR_OV_L (0x1 << 13)
1133 #define RT5659_PWR_OV_R (0x1 << 12)
1135 #define RT5659_PWR_IN_L (0x1 << 9)
1137 #define RT5659_PWR_IN_R (0x1 << 8)
1139 #define RT5659_PWR_MV (0x1 << 7)
1141 #define RT5659_PWR_MIC_DET (0x1 << 5)
1145 #define RT5659_I2S_MS_MASK (0x1 << 15)
1148 #define RT5659_I2S_MS_S (0x1 << 15)
1152 #define RT5659_I2S_O_CP_U_LAW (0x1 << 12)
1157 #define RT5659_I2S_I_CP_U_LAW (0x1 << 10)
1159 #define RT5659_I2S_BP_MASK (0x1 << 8)
1162 #define RT5659_I2S_BP_INV (0x1 << 8)
1166 #define RT5659_I2S_DL_20 (0x1 << 4)
1172 #define RT5659_I2S_DF_LEFT (0x1)
1182 #define RT5659_I2S_PD1_2 (0x1 << 12)
1189 #define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)
1192 #define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)
1196 #define RT5659_I2S_PD2_2 (0x1 << 8)
1203 #define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)
1206 #define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)
1210 #define RT5659_I2S_PD3_2 (0x1 << 4)
1220 #define RT5659_DAC_OSR_64 (0x1 << 2)
1226 #define RT5659_ADC_OSR_64 (0x1)
1231 #define RT5659_DMIC_1_EN_MASK (0x1 << 15)
1234 #define RT5659_DMIC_1_EN (0x1 << 15)
1235 #define RT5659_DMIC_2_EN_MASK (0x1 << 14)
1238 #define RT5659_DMIC_2_EN (0x1 << 14)
1239 #define RT5659_DMIC_1L_LH_MASK (0x1 << 13)
1242 #define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)
1243 #define RT5659_DMIC_1R_LH_MASK (0x1 << 12)
1246 #define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)
1250 #define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)
1258 #define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)
1274 #define RT5659_SCLK_SRC_PLL1 (0x1 << 14)
1279 #define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)
1282 #define RT5659_PLL1_PD_MASK (0x1 << 3)
1285 #define RT5659_PLL1_PD_2 (0x1 << 3)
1301 #define RT5659_PLL_M_BP (0x1 << 11)
1305 #define RT5659_I2S3_ASRC_MASK (0x1 << 13)
1307 #define RT5659_I2S2_ASRC_MASK (0x1 << 12)
1309 #define RT5659_I2S1_ASRC_MASK (0x1 << 11)
1311 #define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)
1313 #define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)
1315 #define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)
1317 #define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)
1319 #define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)
1321 #define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)
1323 #define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)
1325 #define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)
1327 #define RT5659_ADC_MONO_R_ASRC_MASK (0x1)
1357 #define RT5659_SMT_TRIG_MASK (0x1 << 15)
1360 #define RT5659_SMT_TRIG_EN (0x1 << 15)
1361 #define RT5659_HP_L_SMT_MASK (0x1 << 9)
1364 #define RT5659_HP_L_SMT_EN (0x1 << 9)
1365 #define RT5659_HP_R_SMT_MASK (0x1 << 8)
1368 #define RT5659_HP_R_SMT_EN (0x1 << 8)
1369 #define RT5659_HP_CD_PD_MASK (0x1 << 7)
1372 #define RT5659_HP_CD_PD_EN (0x1 << 7)
1373 #define RT5659_RSTN_MASK (0x1 << 6)
1376 #define RT5659_RSTN_EN (0x1 << 6)
1377 #define RT5659_RSTP_MASK (0x1 << 5)
1380 #define RT5659_RSTP_EN (0x1 << 5)
1381 #define RT5659_HP_CO_MASK (0x1 << 4)
1384 #define RT5659_HP_CO_EN (0x1 << 4)
1385 #define RT5659_HP_CP_MASK (0x1 << 3)
1388 #define RT5659_HP_CP_PU (0x1 << 3)
1389 #define RT5659_HP_SG_MASK (0x1 << 2)
1392 #define RT5659_HP_SG_EN (0x1 << 2)
1393 #define RT5659_HP_DP_MASK (0x1 << 1)
1396 #define RT5659_HP_DP_PU (0x1 << 1)
1397 #define RT5659_HP_CB_MASK (0x1)
1400 #define RT5659_HP_CB_PU (0x1)
1403 #define RT5659_DEPOP_MASK (0x1 << 13)
1406 #define RT5659_DEPOP_MAN (0x1 << 13)
1407 #define RT5659_RAMP_MASK (0x1 << 12)
1410 #define RT5659_RAMP_EN (0x1 << 12)
1411 #define RT5659_BPS_MASK (0x1 << 11)
1414 #define RT5659_BPS_EN (0x1 << 11)
1415 #define RT5659_FAST_UPDN_MASK (0x1 << 10)
1418 #define RT5659_FAST_UPDN_EN (0x1 << 10)
1422 #define RT5659_MRES_25MO (0x1 << 8)
1425 #define RT5659_VLO_MASK (0x1 << 7)
1428 #define RT5659_VLO_32V (0x1 << 7)
1429 #define RT5659_DIG_DP_MASK (0x1 << 6)
1432 #define RT5659_DIG_DP_EN (0x1 << 6)
1455 #define RT5659_OSW_L_MASK (0x1 << 11)
1458 #define RT5659_OSW_L_EN (0x1 << 11)
1459 #define RT5659_OSW_R_MASK (0x1 << 10)
1462 #define RT5659_OSW_R_EN (0x1 << 10)
1466 #define RT5659_PM_HP_MV (0x1 << 8)
1471 #define RT5659_IB_HP_25IL (0x1 << 6)
1476 #define RT5659_PVDD_DET_MASK (0x1 << 15)
1479 #define RT5659_PVDD_DET_EN (0x1 << 15)
1480 #define RT5659_SPK_AG_MASK (0x1 << 14)
1483 #define RT5659_SPK_AG_EN (0x1 << 14)
1486 #define RT5659_MIC1_BS_MASK (0x1 << 15)
1489 #define RT5659_MIC1_BS_75AV (0x1 << 15)
1490 #define RT5659_MIC2_BS_MASK (0x1 << 14)
1493 #define RT5659_MIC2_BS_75AV (0x1 << 14)
1494 #define RT5659_MIC1_CLK_MASK (0x1 << 13)
1497 #define RT5659_MIC1_CLK_EN (0x1 << 13)
1498 #define RT5659_MIC2_CLK_MASK (0x1 << 12)
1501 #define RT5659_MIC2_CLK_EN (0x1 << 12)
1502 #define RT5659_MIC1_OVCD_MASK (0x1 << 11)
1505 #define RT5659_MIC1_OVCD_EN (0x1 << 11)
1509 #define RT5659_MIC1_OVTH_1500UA (0x1 << 9)
1511 #define RT5659_MIC2_OVCD_MASK (0x1 << 8)
1514 #define RT5659_MIC2_OVCD_EN (0x1 << 8)
1518 #define RT5659_MIC2_OVTH_1500UA (0x1 << 6)
1520 #define RT5659_PWR_MB_MASK (0x1 << 5)
1523 #define RT5659_PWR_MB_PU (0x1 << 5)
1524 #define RT5659_PWR_CLK25M_MASK (0x1 << 4)
1527 #define RT5659_PWR_CLK25M_PU (0x1 << 4)
1530 #define RT5659_M_BST1_RM2_L (0x1 << 5)
1532 #define RT5659_M_BST2_RM2_L (0x1 << 4)
1534 #define RT5659_M_BST3_RM2_L (0x1 << 3)
1536 #define RT5659_M_BST4_RM2_L (0x1 << 2)
1538 #define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)
1540 #define RT5659_M_SPKVOL_RM2_L (0x1)
1544 #define RT5659_M_BST1_RM2_R (0x1 << 5)
1546 #define RT5659_M_BST2_RM2_R (0x1 << 4)
1548 #define RT5659_M_BST3_RM2_R (0x1 << 3)
1550 #define RT5659_M_BST4_RM2_R (0x1 << 2)
1552 #define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)
1554 #define RT5659_M_MONOVOL_RM2_R (0x1)
1558 #define RT5659_POW_CLSD_DB_MASK (0x1 << 9)
1559 #define RT5659_POW_CLSD_DB_EN (0x1 << 9)
1564 #define RT5659_EQ_SRC_ADC (0x1 << 15)
1565 #define RT5659_EQ_UPD (0x1 << 14)
1567 #define RT5659_EQ_CD_MASK (0x1 << 13)
1570 #define RT5659_EQ_CD_EN (0x1 << 13)
1574 #define RT5659_EQ_DITH_LSB (0x1 << 8)
1579 #define RT5659_JD1_1_EN_MASK (0x1 << 15)
1582 #define RT5659_JD1_1_EN (0x1 << 15)
1583 #define RT5659_JD1_2_EN_MASK (0x1 << 12)
1586 #define RT5659_JD1_2_EN (0x1 << 12)
1587 #define RT5659_IL_IRQ_MASK (0x1 << 3)
1589 #define RT5659_IL_IRQ_EN (0x1 << 3)
1592 #define RT5659_IRQ_JD_EN (0x1 << 3)
1596 #define RT5659_GP1_PIN_MASK (0x1 << 15)
1599 #define RT5659_GP1_PIN_IRQ (0x1 << 15)
1600 #define RT5659_GP2_PIN_MASK (0x1 << 14)
1603 #define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)
1604 #define RT5659_GP3_PIN_MASK (0x1 << 13)
1607 #define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)
1608 #define RT5659_GP4_PIN_MASK (0x1 << 12)
1611 #define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)
1612 #define RT5659_GP5_PIN_MASK (0x1 << 11)
1615 #define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)
1616 #define RT5659_GP6_PIN_MASK (0x1 << 10)
1619 #define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)
1620 #define RT5659_GP7_PIN_MASK (0x1 << 9)
1623 #define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)
1624 #define RT5659_GP8_PIN_MASK (0x1 << 8)
1627 #define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)
1628 #define RT5659_GP9_PIN_MASK (0x1 << 7)
1631 #define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)
1632 #define RT5659_GP10_PIN_MASK (0x1 << 6)
1635 #define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)
1636 #define RT5659_GP11_PIN_MASK (0x1 << 5)
1639 #define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)
1640 #define RT5659_GP12_PIN_MASK (0x1 << 4)
1643 #define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)
1647 #define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)
1653 #define RT5659_GP15_PIN_DMIC3_SCL (0x1)
1658 #define RT5659_GP1_PF_OUT (0x1 << 2)
1659 #define RT5659_GP1_PF_MASK (0x1 << 2)
1663 #define RT5659_I2S2_PIN_MASK (0x1 << 15)
1666 #define RT5659_I2S2_PIN_GPIO (0x1 << 15)
1669 #define RT5659_SV_MASK (0x1 << 15)
1672 #define RT5659_SV_EN (0x1 << 15)
1673 #define RT5659_OUT_SV_MASK (0x1 << 13)
1676 #define RT5659_OUT_SV_EN (0x1 << 13)
1677 #define RT5659_HP_SV_MASK (0x1 << 12)
1680 #define RT5659_HP_SV_EN (0x1 << 12)
1681 #define RT5659_ZCD_DIG_MASK (0x1 << 11)
1684 #define RT5659_ZCD_DIG_EN (0x1 << 11)
1685 #define RT5659_ZCD_MASK (0x1 << 10)
1688 #define RT5659_ZCD_PU (0x1 << 10)
1693 #define RT5659_ZCD_HP_MASK (0x1 << 15)
1696 #define RT5659_ZCD_HP_EN (0x1 << 15)
1699 #define RT5659_4BTN_IL_MASK (0x1 << 15)
1700 #define RT5659_4BTN_IL_EN (0x1 << 15)
1706 #define RT5659_JD1_MODE_1 (0x1 << 0)
1713 #define RT5659_JD_HPO_JD1_1 (0x1)
1721 #define RT5659_AM_MASK (0x1 << 7)
1722 #define RT5659_AM_EN (0x1 << 7)
1723 #define RT5659_AM_DIS (0x1 << 7)
1724 #define RT5659_DIG_GATE_CTRL 0x1
1728 #define RT5659_M_RF_DIG_MASK (0x1 << 12)
1730 #define RT5659_M_RI_DIG (0x1 << 11)
1733 #define RT5659_CKXEN_DAC1_MASK (0x1 << 13)
1735 #define RT5659_CKGEN_DAC1_MASK (0x1 << 12)
1737 #define RT5659_CKXEN_DAC2_MASK (0x1 << 5)
1739 #define RT5659_CKGEN_DAC2_MASK (0x1 << 4)
1743 #define RT5659_CKXEN_ADC1_MASK (0x1 << 13)
1745 #define RT5659_CKGEN_ADC1_MASK (0x1 << 12)
1747 #define RT5659_CKXEN_ADC2_MASK (0x1 << 5)
1749 #define RT5659_CKGEN_ADC2_MASK (0x1 << 4)
1753 #define RT5659_AD2DA_LB_MASK (0x1 << 9)
1757 #define RT5659_NG2_EN_MASK (0x1 << 15)
1758 #define RT5659_NG2_EN (0x1 << 15)