soc/codecs/rt5640.c

39 #define RT5640_PR_BASE (RT5640_PR_RANGE_BASE + (0 * RT5640_PR_SPACING))
42 	{ .name = "PR", .range_min = RT5640_PR_BASE,
43 	  .range_max = RT5640_PR_BASE + 0xb4,
52 	{RT5640_PR_BASE + 0x3d,	0x3600},
53 	{RT5640_PR_BASE + 0x12,	0x0aa8},
54 	{RT5640_PR_BASE + 0x14,	0x0aaa},
55 	{RT5640_PR_BASE + 0x21,	0xe0e0},
56 	{RT5640_PR_BASE + 0x23,	0x1804},
921 	regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
928 	regmap_write(rt5640->regmap, RT5640_PR_BASE + RT5640_HP_DCC_INT1,
958 	regmap_write(rt5640->regmap, RT5640_PR_BASE +
963 	regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
2444 	snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,