Lines Matching defs:priv
21 static void mt6359_set_gpio_smt(struct mt6359_priv *priv)
24 regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0);
27 static void mt6359_set_gpio_driving(struct mt6359_priv *priv)
30 regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888);
31 regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888);
32 regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88);
35 static void mt6359_set_playback_gpio(struct mt6359_priv *priv)
38 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
42 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
43 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
46 static void mt6359_reset_playback_gpio(struct mt6359_priv *priv)
53 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
54 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0);
57 static void mt6359_set_capture_gpio(struct mt6359_priv *priv)
60 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
64 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
67 static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
75 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
77 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
79 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
81 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
86 static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
88 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
94 static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
97 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
103 static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
105 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
111 static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
113 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
117 static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
119 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
124 static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)
126 switch (priv->mtkaif_protocol) {
129 regmap_update_bits(priv->regmap,
133 regmap_update_bits(priv->regmap,
136 regmap_update_bits(priv->regmap,
142 regmap_update_bits(priv->regmap,
146 regmap_update_bits(priv->regmap,
153 regmap_update_bits(priv->regmap,
157 regmap_update_bits(priv->regmap,
164 static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
167 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
174 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
176 priv->mtkaif_protocol = mtkaif_protocol;
182 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
184 mt6359_set_playback_gpio(priv);
185 mt6359_set_capture_gpio(priv);
186 mt6359_mtkaif_tx_enable(priv);
188 mt6359_set_dcxo(priv, true);
189 mt6359_set_aud_global_bias(priv, true);
190 mt6359_set_clksq(priv, true);
191 mt6359_set_topck(priv, true);
194 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
197 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
200 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
208 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
211 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
214 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
217 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
221 mt6359_set_topck(priv, false);
222 mt6359_set_clksq(priv, false);
223 mt6359_set_aud_global_bias(priv, false);
224 mt6359_set_dcxo(priv, false);
226 mt6359_mtkaif_tx_disable(priv);
227 mt6359_reset_playback_gpio(priv);
228 mt6359_reset_capture_gpio(priv);
235 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
237 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
240 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
243 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
249 static void zcd_disable(struct mt6359_priv *priv)
251 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
254 static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
262 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
265 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
272 static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)
280 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
286 static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)
292 if (priv->hp_hifi_mode) {
296 regmap_update_bits(priv->regmap,
304 static void hp_pull_down(struct mt6359_priv *priv, bool enable)
310 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
317 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
331 static void headset_volume_ramp(struct mt6359_priv *priv,
337 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
342 dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to);
356 regmap_update_bits(priv->regmap,
372 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
382 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
383 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
386 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
387 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
390 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
393 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
396 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
399 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
411 regmap_read(priv->regmap, MT6359_ZCD_CON2, ®);
412 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
414 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
416 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
417 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
420 regmap_read(priv->regmap, MT6359_ZCD_CON1, ®);
421 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
423 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
425 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
426 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
429 regmap_read(priv->regmap, MT6359_ZCD_CON3, ®);
430 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
432 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
435 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, ®);
436 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
438 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
441 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, ®);
442 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
444 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
447 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, ®);
448 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
450 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
462 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
473 struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);
480 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
482 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
486 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
488 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
492 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
821 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
823 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
828 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
830 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
832 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
834 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b);
836 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
839 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
845 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
846 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
855 static void mtk_hp_enable(struct mt6359_priv *priv)
857 if (priv->hp_hifi_mode) {
859 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
864 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
867 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
872 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
877 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
880 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
887 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
891 if (priv->dl_rate[MT6359_AIF_1] >= 96000)
892 regmap_update_bits(priv->regmap,
897 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
900 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
903 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
907 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
909 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
911 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
913 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
916 hp_in_pair_current(priv, true);
919 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
921 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
924 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
926 hp_main_output_ramp(priv, true);
929 hp_aux_feedback_loop_gain_ramp(priv, true);
931 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
934 headset_volume_ramp(priv,
936 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
939 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
941 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
945 mt6359_set_decoder_clk(priv, true);
948 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
949 if (priv->hp_hifi_mode) {
951 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
954 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
959 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
961 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
964 hp_pull_down(priv, false);
967 static void mtk_hp_disable(struct mt6359_priv *priv)
970 hp_pull_down(priv, true);
973 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
977 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
981 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
985 mt6359_set_decoder_clk(priv, false);
988 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
990 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
993 headset_volume_ramp(priv,
994 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
998 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
1001 hp_aux_feedback_loop_gain_ramp(priv, false);
1004 hp_main_output_ramp(priv, false);
1007 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
1010 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
1013 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
1016 hp_in_pair_current(priv, false);
1019 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1023 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1027 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1031 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
1034 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1038 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1047 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1051 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1052 __func__, event, priv->dev_counter[device], mux);
1056 priv->dev_counter[device]++;
1058 mtk_hp_enable(priv);
1061 priv->dev_counter[device]--;
1063 mtk_hp_disable(priv);
1077 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1079 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1085 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
1088 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1093 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1096 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1101 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
1104 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
1107 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
1109 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
1112 regmap_write(priv->regmap, MT6359_ZCD_CON3,
1113 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
1116 mt6359_set_decoder_clk(priv, true);
1119 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
1121 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1123 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
1127 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1132 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1136 mt6359_set_decoder_clk(priv, false);
1139 regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
1142 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1146 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1161 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1164 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1170 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
1173 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1178 if (priv->dev_counter[DEVICE_HP] == 0)
1179 regmap_update_bits(priv->regmap,
1184 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1189 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
1192 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
1194 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
1197 regmap_write(priv->regmap, MT6359_ZCD_CON1,
1198 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1201 mt6359_set_decoder_clk(priv, true);
1205 if (priv->dev_counter[DEVICE_HP] > 0) {
1206 dev_info(priv->dev, "%s(), can not enable DAC, hp count %d\n",
1207 __func__, priv->dev_counter[DEVICE_HP]);
1211 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3009);
1213 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
1216 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0117);
1219 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
1221 if (priv->dev_counter[DEVICE_HP] == 0)
1222 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1224 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
1229 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1234 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1239 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1242 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1247 mt6359_set_decoder_clk(priv, false);
1250 regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
1253 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1257 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1272 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1274 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1279 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1282 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1284 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1286 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1291 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1293 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1295 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1297 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1312 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1314 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1320 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1322 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1324 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1327 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
1330 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1332 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1347 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1348 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1350 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1357 regmap_update_bits(priv->regmap,
1362 regmap_update_bits(priv->regmap,
1367 regmap_update_bits(priv->regmap,
1374 regmap_write(priv->regmap,
1377 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1381 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1387 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
1401 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1402 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1404 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1411 regmap_write(priv->regmap,
1414 regmap_write(priv->regmap,
1418 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
1434 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1435 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1437 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1444 regmap_update_bits(priv->regmap,
1449 regmap_update_bits(priv->regmap,
1454 regmap_update_bits(priv->regmap,
1461 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1465 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1471 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
1485 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1487 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1491 mt6359_mtkaif_tx_enable(priv);
1494 mt6359_mtkaif_tx_disable(priv);
1508 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1510 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1515 if (priv->dmic_one_wire_mode)
1516 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1519 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1522 regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
1526 regmap_write(priv->regmap,
1541 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1543 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1548 regmap_write(priv->regmap,
1550 regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
1554 regmap_write(priv->regmap,
1569 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1571 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1577 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1593 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1595 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1601 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1617 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1619 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1625 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1641 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1644 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1645 priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
1654 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1657 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1658 priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
1667 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1670 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1671 priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
1680 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1681 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1682 unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
1687 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1690 mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1693 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1702 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1709 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1715 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1722 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1738 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1739 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1740 unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
1745 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1749 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1752 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1761 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1768 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1774 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1781 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1797 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1798 int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
1799 unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
1805 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1808 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1817 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1824 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1830 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1837 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1886 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1890 hp_pull_down(priv, true);
1893 hp_pull_down(priv, false);
1907 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1912 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
1916 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
1930 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1936 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
1950 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1955 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1962 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1977 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1982 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1985 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
1987 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1990 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1995 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1997 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
2011 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2016 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
2018 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1);
2020 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
2022 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b);
2026 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
2027 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
2041 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2045 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
2417 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2419 if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
2420 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
2421 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
2649 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2653 dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
2657 priv->dl_rate[id] = rate;
2659 priv->ul_rate[id] = rate;
2668 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2670 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2672 mt6359_set_playback_gpio(priv);
2674 mt6359_set_capture_gpio(priv);
2683 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2685 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2687 mt6359_reset_playback_gpio(priv);
2689 mt6359_reset_capture_gpio(priv);
2757 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2760 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2767 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
2772 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2775 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2779 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
2783 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
2788 mt6359_set_gpio_smt(priv);
2789 mt6359_set_gpio_driving(priv);
2790 mt6359_reset_playback_gpio(priv);
2791 mt6359_reset_capture_gpio(priv);
2794 priv->hp_hifi_mode = 0;
2797 zcd_disable(priv);
2800 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2809 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2811 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2864 static int mt6359_parse_dt(struct mt6359_priv *priv)
2867 struct device *dev = priv->dev;
2878 &priv->dmic_one_wire_mode);
2880 dev_info(priv->dev,
2883 priv->dmic_one_wire_mode = 0;
2887 &priv->mux_select[MUX_MIC_TYPE_0]);
2889 dev_info(priv->dev,
2892 priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE;
2896 &priv->mux_select[MUX_MIC_TYPE_1]);
2898 dev_info(priv->dev,
2901 priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE;
2905 &priv->mux_select[MUX_MIC_TYPE_2]);
2908 dev_info(priv->dev,
2911 priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE;
2919 struct mt6359_priv *priv;
2926 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2927 if (!priv)
2930 priv->regmap = mt6397->regmap;
2931 if (IS_ERR(priv->regmap))
2932 return PTR_ERR(priv->regmap);
2934 dev_set_drvdata(&pdev->dev, priv);
2935 priv->dev = &pdev->dev;
2937 ret = mt6359_parse_dt(priv);