soc/codecs/adau1372.c

24 #include "adau1372.h"
27 struct adau1372 {
576 	struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
582 		adau1372->clock_provider = true;
586 		adau1372->clock_provider = false;
630 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
631 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
641 	struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
657 	slot_width = adau1372->slot_width;
673 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
674 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
682 	struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
688 		regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
690 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
691 		adau1372->slot_width = 0;
714 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
718 		if (adau1372->clock_provider)
719 			adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
721 			adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
725 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
731 	adau1372->slot_width = width;
733 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
734 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
737 	regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
744 	struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
752 	return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
757 	struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
760 				   &adau1372->rate_constraints);
765 static void adau1372_enable_pll(struct adau1372 *adau1372)
770 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
775 		ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
782 		dev_err(adau1372->dev, "Failed to lock PLL\n");
785 static void adau1372_set_power(struct adau1372 *adau1372, bool enable)
787 	if (adau1372->enabled == enable)
793 		clk_prepare_enable(adau1372->mclk);
794 		if (adau1372->pd_gpio)
795 			gpiod_set_value(adau1372->pd_gpio, 0);
797 		if (adau1372->switch_mode)
798 			adau1372->switch_mode(adau1372->dev);
800 		regcache_cache_only(adau1372->regmap, false);
806 		if (adau1372->use_pll) {
807 			adau1372_enable_pll(adau1372);
811 		regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
813 		regcache_sync(adau1372->regmap);
815 		if (adau1372->pd_gpio) {
821 			gpiod_set_value(adau1372->pd_gpio, 1);
822 			regcache_mark_dirty(adau1372->regmap);
824 			regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
827 		clk_disable_unprepare(adau1372->mclk);
828 		regcache_cache_only(adau1372->regmap, true);
831 	adau1372->enabled = enable;
837 	struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
845 		adau1372_set_power(adau1372, true);
848 		adau1372_set_power(adau1372, false);
879 	.name = "adau1372",
900 static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
911 		regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
919 	struct adau1372 *adau1372;
927 	adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
928 	if (!adau1372)
931 	adau1372->mclk = devm_clk_get(dev, "mclk");
932 	if (IS_ERR(adau1372->mclk))
933 		return PTR_ERR(adau1372->mclk);
935 	adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
936 	if (IS_ERR(adau1372->pd_gpio))
937 		return PTR_ERR(adau1372->pd_gpio);
939 	adau1372->regmap = regmap;
940 	adau1372->switch_mode = switch_mode;
941 	adau1372->dev = dev;
942 	adau1372->rate_constraints.list = adau1372_rates;
943 	adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
944 	adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
946 	dev_set_drvdata(dev, adau1372);
953 	rate = clk_get_rate(adau1372->mclk);
964 		ret = adau1372_setup_pll(adau1372, rate);
967 		adau1372->use_pll = true;
1065 	{ .compatible = "adi,adau1372" },