1289 #define MLX5_CAP_GEN(mdev, cap) \  argument
1290 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1292 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1293 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1295 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1296 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1298 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1299 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1301 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1302 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1304 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1305 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1307 #define MLX5_CAP_ETH(mdev, cap) \  argument
1309 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1311 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1313 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1315 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1316 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1318 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1319 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1321 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1322 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1324 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1325 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1327 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1328 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1330 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1331 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1333 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1334 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1336 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1337 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1339 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1340 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1342 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1343 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1345 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1346 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1348 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1349 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1351 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \  argument
1352 	MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1354 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \  argument
1355 	MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1357 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1359 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1361 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1362 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1364 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1365 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1367 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1368 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1370 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1371 	MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1373 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1374 		MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1376 #define MLX5_CAP_ESW(mdev, cap) \  argument
1378 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1380 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1382 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1384 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1386 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1388 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1390 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1392 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1394 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1396 #define MLX5_CAP_ADV_RDMA(mdev, cap) \  argument
1398 		 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1400 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1401 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1403 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1404 	MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1406 #define MLX5_CAP_ODP(mdev, cap)\  argument
1407 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1409 #define MLX5_CAP_ODP_SCHEME(mdev, cap)                                \  argument
1413 			  memory_page_fault_scheme_cap.cap) :         \
1415 			  transport_page_fault_scheme_cap.cap))
1417 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1418 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1420 #define MLX5_CAP_QOS(mdev, cap)\  argument
1421 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1423 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1424 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1453 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1454 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1456 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1457 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1459 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1460 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1462 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1463 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1465 #define MLX5_CAP_TLS(mdev, cap) \  argument
1466 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1468 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1469 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1471 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1473 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1475 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1477 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1479 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1480 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1482 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1483 	MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1485 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1486 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1488 #define MLX5_CAP_SHAMPO(mdev, cap) \  argument
1489 	MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
1491 #define MLX5_CAP_PSP(mdev, cap)\  argument
1492 	MLX5_GET(psp_cap, (mdev)->caps.hca[MLX5_CAP_PSP]->cur, cap)