76 	SCFCR,		/* FIFO Control Register */  enumerator
332 			[SCFCR]		= { 0x0c,  8 },
356 			[SCFCR]		= { 0x18, 16 },
382 			[SCFCR]		= { 0x18, 16 },
410 			[SCFCR]		= { 0x18, 16 },
439 			[SCFCR]		= { 0x0C, 16 },
472 			[SCFCR]		= { 0x0c, 16 },
499 			[SCFCR]		= { 0x0c,  8 },
523 			[SCFCR]		= { 0x18, 16 },
550 			[SCFCR]		= { 0x18, 16 },
578 			[SCFCR]		= { 0x18, 16 },
610 			[SCFCR]		= { 0x18, 16 },
636 			[SCFCR]		= { 0x18, 16 },
665 			[SCFCR]		= { 0x18, 16 },
1305 	sci_serial_out(port, SCFCR,  in scif_set_rtrg()
1306 		       (sci_serial_in(port, SCFCR) &  in scif_set_rtrg()
1317 		return (sci_serial_in(port, SCFCR) &  in scif_rtrg_enabled()
2358 		reg = sci_getreg(port, SCFCR);  in sci_set_mctrl()
2360 			sci_serial_out(port, SCFCR,  in sci_set_mctrl()
2361 				       sci_serial_in(port, SCFCR) | SCFCR_LOOP);  in sci_set_mctrl()
2372 			sci_serial_out(port, SCFCR,  in sci_set_mctrl()
2373 				       sci_serial_in(port, SCFCR) & ~SCFCR_MCE);  in sci_set_mctrl()
2386 			sci_serial_out(port, SCFCR,  in sci_set_mctrl()
2387 				       sci_serial_in(port, SCFCR) | SCFCR_MCE);  in sci_set_mctrl()
2651 	reg = sci_getreg(port, SCFCR);  in sci_reset()
2653 		sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);  in sci_reset()
2870 	reg = sci_getreg(port, SCFCR);  in sci_set_termios()
2872 		unsigned short ctrl = sci_serial_in(port, SCFCR);  in sci_set_termios()
2889 		sci_serial_out(port, SCFCR, ctrl);  in sci_set_termios()
3079 	if (sci_getreg(port, SCFCR)->size)  in sci_console_save()
3080 		regs->scfcr = sci_serial_in(port, SCFCR);  in sci_console_save()
3108 	if (sci_getreg(port, SCFCR)->size)  in sci_console_restore()
3109 		sci_serial_out(port, SCFCR, regs->scfcr);  in sci_console_restore()