Lines Matching refs:msm_write
196 void msm_write(struct uart_port *port, unsigned int val, unsigned int off) in msm_write() function
212 msm_write(port, 0x06, MSM_UART_MREG); in msm_serial_set_mnd_regs_tcxo()
213 msm_write(port, 0xF1, MSM_UART_NREG); in msm_serial_set_mnd_regs_tcxo()
214 msm_write(port, 0x0F, MSM_UART_DREG); in msm_serial_set_mnd_regs_tcxo()
215 msm_write(port, 0x1A, MSM_UART_MNDREG); in msm_serial_set_mnd_regs_tcxo()
224 msm_write(port, 0x18, MSM_UART_MREG); in msm_serial_set_mnd_regs_tcxoby4()
225 msm_write(port, 0xF6, MSM_UART_NREG); in msm_serial_set_mnd_regs_tcxoby4()
226 msm_write(port, 0x0F, MSM_UART_DREG); in msm_serial_set_mnd_regs_tcxoby4()
227 msm_write(port, 0x0A, MSM_UART_MNDREG); in msm_serial_set_mnd_regs_tcxoby4()
275 msm_write(port, val, UARTDM_DMEN); in msm_stop_dma()
420 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR); in msm_wait_for_xmitr()
428 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_stop_tx()
441 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_start_tx()
447 msm_write(port, count, UARTDM_NCF_TX); in msm_reset_dm_count()
474 msm_write(port, val, UARTDM_DMEN); in msm_complete_tx_dma()
477 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); in msm_complete_tx_dma()
478 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR); in msm_complete_tx_dma()
487 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_complete_tx_dma()
537 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_handle_tx_dma()
543 msm_write(port, val, UARTDM_DMEN); in msm_handle_tx_dma()
548 msm_write(port, val, UARTDM_DMEN); in msm_handle_tx_dma()
577 msm_write(port, val, UARTDM_DMEN); in msm_complete_rx_dma()
582 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); in msm_complete_rx_dma()
665 msm_write(uart, msm_port->imr, MSM_UART_IMR); in msm_start_rx_dma()
671 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); in msm_start_rx_dma()
672 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); in msm_start_rx_dma()
678 msm_write(uart, val, UARTDM_DMEN); in msm_start_rx_dma()
680 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); in msm_start_rx_dma()
683 msm_write(uart, val, UARTDM_DMEN); in msm_start_rx_dma()
694 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); in msm_start_rx_dma()
695 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR); in msm_start_rx_dma()
697 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); in msm_start_rx_dma()
698 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); in msm_start_rx_dma()
699 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); in msm_start_rx_dma()
703 msm_write(uart, msm_port->imr, MSM_UART_IMR); in msm_start_rx_dma()
712 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_stop_rx()
723 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_enable_ms()
737 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); in msm_handle_rx_dm()
790 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); in msm_handle_rx_dm()
791 msm_write(port, 0xFFFFFF, UARTDM_DMRX); in msm_handle_rx_dm()
792 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); in msm_handle_rx_dm()
811 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); in msm_handle_rx()
947 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); in msm_handle_delta_cts()
962 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */ in msm_uart_irq()
966 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR); in msm_uart_irq()
972 msm_write(port, val, MSM_UART_CR); in msm_uart_irq()
974 msm_write(port, val, MSM_UART_CR); in msm_uart_irq()
991 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */ in msm_uart_irq()
1013 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); in msm_reset()
1014 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); in msm_reset()
1015 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); in msm_reset()
1016 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR); in msm_reset()
1017 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); in msm_reset()
1018 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); in msm_reset()
1021 msm_write(port, mr, MSM_UART_MR1); in msm_reset()
1025 msm_write(port, 0, UARTDM_DMEN); in msm_reset()
1036 msm_write(port, mr, MSM_UART_MR1); in msm_set_mctrl()
1037 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); in msm_set_mctrl()
1040 msm_write(port, mr, MSM_UART_MR1); in msm_set_mctrl()
1047 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR); in msm_break_ctl()
1049 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR); in msm_break_ctl()
1147 msm_write(port, entry->code, MSM_UART_CSR); in msm_set_baud_rate()
1161 msm_write(port, watermark, MSM_UART_IPR); in msm_set_baud_rate()
1165 msm_write(port, watermark, MSM_UART_RFWR); in msm_set_baud_rate()
1168 msm_write(port, 10, MSM_UART_TFWR); in msm_set_baud_rate()
1170 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR); in msm_set_baud_rate()
1174 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR); in msm_set_baud_rate()
1180 msm_write(port, msm_port->imr, MSM_UART_IMR); in msm_set_baud_rate()
1183 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); in msm_set_baud_rate()
1184 msm_write(port, 0xFFFFFF, UARTDM_DMRX); in msm_set_baud_rate()
1185 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); in msm_set_baud_rate()
1229 msm_write(port, data, MSM_UART_MR1); in msm_startup()
1259 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */ in msm_shutdown()
1327 msm_write(port, mr, MSM_UART_MR2); in msm_set_termios()
1336 msm_write(port, mr, MSM_UART_MR1); in msm_set_termios()
1477 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR); in msm_poll_get_char_dm()
1481 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); in msm_poll_get_char_dm()
1482 msm_write(port, 0xFFFFFF, UARTDM_DMRX); in msm_poll_get_char_dm()
1483 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); in msm_poll_get_char_dm()
1505 msm_write(port, 0, MSM_UART_IMR); in msm_poll_get_char()
1513 msm_write(port, imr, MSM_UART_IMR); in msm_poll_get_char()
1525 msm_write(port, 0, MSM_UART_IMR); in msm_poll_put_char()
1535 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF); in msm_poll_put_char()
1542 msm_write(port, imr, MSM_UART_IMR); in msm_poll_put_char()
1750 msm_write(&device->port, 0, UARTDM_DMEN); in msm_serial_early_console_setup_dm()
1751 msm_write(&device->port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); in msm_serial_early_console_setup_dm()
1752 msm_write(&device->port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); in msm_serial_early_console_setup_dm()
1753 msm_write(&device->port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR); in msm_serial_early_console_setup_dm()