drivers/spi/spi-sun6i.c

117 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
119 	return readl(sspi->base_addr + reg);
122 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
124 	writel(value, sspi->base_addr + reg);
127 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
129 	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
134 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
136 	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
141 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
143 	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
146 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
149 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
155 	len = sun6i_spi_get_rx_fifo_count(sspi);
158 		byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
159 		if (sspi->rx_buf)
160 			*sspi->rx_buf++ = byte;
164 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
171 	cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
173 	len = min((int)cnt, sspi->len);
176 		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
177 		writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
178 		sspi->len--;
184 	struct sun6i_spi *sspi = spi_controller_get_devdata(spi->controller);
187 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
196 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
206 	struct sun6i_spi *sspi = param;
208 	complete(&sspi->dma_rx_done);
211 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
215 	struct spi_controller *host = sspi->host;
221 			.src_addr = sspi->dma_addr_rx,
235 		rxdesc->callback_param = sspi;
243 			.dst_addr = sspi->dma_addr_tx,
279 	struct sun6i_spi *sspi = spi_controller_get_devdata(host);
292 	reinit_completion(&sspi->done);
293 	reinit_completion(&sspi->dma_rx_done);
294 	sspi->tx_buf = tfr->tx_buf;
295 	sspi->rx_buf = tfr->rx_buf;
296 	sspi->len = tfr->len;
300 	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
303 	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
315 		trig_level = sspi->cfg->fifo_depth / 4 * 3;
322 		trig_level = sspi->cfg->fifo_depth / 2;
333 	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
339 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
360 	if (sspi->rx_buf) {
370 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
372 	if (sspi->cfg->has_clk_ctl) {
373 		unsigned int mclk_rate = clk_get_rate(sspi->mclk);
377 			clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
378 			mclk_rate = clk_get_rate(sspi->mclk);
406 		sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
408 		clk_set_rate(sspi->mclk, tfr->speed_hz);
409 		tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
420 		reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
428 		sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
432 	reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
434 	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
437 	if (sspi->tx_buf) {
457 	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
458 	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
459 	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
463 		sun6i_spi_fill_fifo(sspi);
465 		ret = sun6i_spi_prepare_dma(sspi, tfr);
478 		if (rx_len > sspi->cfg->fifo_depth)
480 		if (tx_len > sspi->cfg->fifo_depth)
484 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
487 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
488 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
492 	time_left = wait_for_completion_timeout(&sspi->done,
496 		sun6i_spi_drain_fifo(sspi);
503 			time_left = wait_for_completion_timeout(&sspi->dma_rx_done,
519 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
531 	struct sun6i_spi *sspi = dev_id;
532 	u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
536 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
537 		complete(&sspi->done);
543 		sun6i_spi_drain_fifo(sspi);
545 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
551 		sun6i_spi_fill_fifo(sspi);
553 		if (!sspi->len)
555 			sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
558 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
569 	struct sun6i_spi *sspi = spi_controller_get_devdata(host);
572 	ret = clk_prepare_enable(sspi->hclk);
578 	ret = clk_prepare_enable(sspi->mclk);
584 	ret = reset_control_deassert(sspi->rstc);
590 	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
596 	clk_disable_unprepare(sspi->mclk);
598 	clk_disable_unprepare(sspi->hclk);
606 	struct sun6i_spi *sspi = spi_controller_get_devdata(host);
608 	reset_control_assert(sspi->rstc);
609 	clk_disable_unprepare(sspi->mclk);
610 	clk_disable_unprepare(sspi->hclk);
619 	struct sun6i_spi *sspi = spi_controller_get_devdata(host);
626 	return xfer->len > sspi->cfg->fifo_depth;
632 	struct sun6i_spi *sspi;
643 	sspi = spi_controller_get_devdata(host);
645 	sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
646 	if (IS_ERR(sspi->base_addr)) {
647 		ret = PTR_ERR(sspi->base_addr);
658 			       0, "sun6i-spi", sspi);
664 	sspi->host = host;
665 	sspi->cfg = of_device_get_match_data(&pdev->dev);
674 			  sspi->cfg->mode_bits;
680 	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
681 	if (IS_ERR(sspi->hclk)) {
683 		ret = PTR_ERR(sspi->hclk);
687 	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
688 	if (IS_ERR(sspi->mclk)) {
690 		ret = PTR_ERR(sspi->mclk);
694 	init_completion(&sspi->done);
695 	init_completion(&sspi->dma_rx_done);
697 	sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
698 	if (IS_ERR(sspi->rstc)) {
700 		ret = PTR_ERR(sspi->rstc);
726 		sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
727 		sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;