Lines Matching defs:sspi

90 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
92 return readl(sspi->base_addr + reg);
95 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
97 writel(value, sspi->base_addr + reg);
100 static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
102 u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
109 static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
111 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
114 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
117 static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
119 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
122 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
125 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
131 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
145 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
153 len = min3(len, (int)cnt, sspi->len);
156 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
157 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
158 sspi->len--;
164 struct sun4i_spi *sspi = spi_controller_get_devdata(spi->controller);
167 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
196 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
208 struct sun4i_spi *sspi = spi_controller_get_devdata(host);
223 reinit_completion(&sspi->done);
224 sspi->tx_buf = tfr->tx_buf;
225 sspi->rx_buf = tfr->rx_buf;
226 sspi->len = tfr->len;
229 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
232 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
235 sun4i_spi_write(sspi, SUN4I_CTL_REG,
262 if (sspi->rx_buf)
270 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
273 mclk_rate = clk_get_rate(sspi->mclk);
275 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
276 mclk_rate = clk_get_rate(sspi->mclk);
304 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
307 if (sspi->tx_buf)
311 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
312 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
319 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
322 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
326 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
329 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
330 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
334 time_left = wait_for_completion_timeout(&sspi->done,
348 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
355 struct sun4i_spi *sspi = dev_id;
356 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
360 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
361 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
362 complete(&sspi->done);
368 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
370 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
376 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
378 if (!sspi->len)
380 sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
383 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
394 struct sun4i_spi *sspi = spi_controller_get_devdata(host);
397 ret = clk_prepare_enable(sspi->hclk);
403 ret = clk_prepare_enable(sspi->mclk);
409 sun4i_spi_write(sspi, SUN4I_CTL_REG,
415 clk_disable_unprepare(sspi->hclk);
423 struct sun4i_spi *sspi = spi_controller_get_devdata(host);
425 clk_disable_unprepare(sspi->mclk);
426 clk_disable_unprepare(sspi->hclk);
434 struct sun4i_spi *sspi;
444 sspi = spi_controller_get_devdata(host);
446 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
447 if (IS_ERR(sspi->base_addr)) {
448 ret = PTR_ERR(sspi->base_addr);
459 0, "sun4i-spi", sspi);
465 sspi->host = host;
478 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
479 if (IS_ERR(sspi->hclk)) {
481 ret = PTR_ERR(sspi->hclk);
485 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
486 if (IS_ERR(sspi->mclk)) {
488 ret = PTR_ERR(sspi->mclk);
492 init_completion(&sspi->done);