Lines Matching refs:sdd
115 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ argument
116 __ffs((sdd)->tx_fifomask))
117 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ argument
118 __ffs((sdd)->rx_fifomask))
229 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_flush_fifo() argument
231 void __iomem *regs = sdd->regs; in s3c64xx_flush_fifo()
250 } while (TX_FIFO_LVL(val, sdd) && --loops); in s3c64xx_flush_fifo()
253 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); in s3c64xx_flush_fifo()
259 if (RX_FIFO_LVL(val, sdd)) in s3c64xx_flush_fifo()
266 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); in s3c64xx_flush_fifo()
279 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_dmacb() local
284 sdd = container_of(data, in s3c64xx_spi_dmacb()
287 sdd = container_of(data, in s3c64xx_spi_dmacb()
290 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_dmacb()
293 sdd->state &= ~RXBUSY; in s3c64xx_spi_dmacb()
294 if (!(sdd->state & TXBUSY)) in s3c64xx_spi_dmacb()
295 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
297 sdd->state &= ~TXBUSY; in s3c64xx_spi_dmacb()
298 if (!(sdd->state & RXBUSY)) in s3c64xx_spi_dmacb()
299 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
302 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_dmacb()
308 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_prepare_dma() local
316 sdd = container_of((void *)dma, in s3c64xx_prepare_dma()
318 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; in s3c64xx_prepare_dma()
319 config.src_addr_width = sdd->cur_bpw / 8; in s3c64xx_prepare_dma()
322 sdd = container_of((void *)dma, in s3c64xx_prepare_dma()
324 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; in s3c64xx_prepare_dma()
325 config.dst_addr_width = sdd->cur_bpw / 8; in s3c64xx_prepare_dma()
336 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", in s3c64xx_prepare_dma()
347 dev_err(&sdd->pdev->dev, "DMA submission failed"); in s3c64xx_prepare_dma()
357 struct s3c64xx_spi_driver_data *sdd = in s3c64xx_spi_set_cs() local
360 if (sdd->cntrlr_info->no_cs) in s3c64xx_spi_set_cs()
364 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { in s3c64xx_spi_set_cs()
365 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
367 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
371 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
374 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_set_cs()
376 sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
382 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); in s3c64xx_spi_prepare_transfer() local
384 if (is_polling(sdd)) in s3c64xx_spi_prepare_transfer()
388 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); in s3c64xx_spi_prepare_transfer()
389 if (IS_ERR(sdd->rx_dma.ch)) { in s3c64xx_spi_prepare_transfer()
390 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); in s3c64xx_spi_prepare_transfer()
391 sdd->rx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
395 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); in s3c64xx_spi_prepare_transfer()
396 if (IS_ERR(sdd->tx_dma.ch)) { in s3c64xx_spi_prepare_transfer()
397 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); in s3c64xx_spi_prepare_transfer()
398 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_prepare_transfer()
399 sdd->tx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
400 sdd->rx_dma.ch = NULL; in s3c64xx_spi_prepare_transfer()
404 spi->dma_rx = sdd->rx_dma.ch; in s3c64xx_spi_prepare_transfer()
405 spi->dma_tx = sdd->tx_dma.ch; in s3c64xx_spi_prepare_transfer()
412 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); in s3c64xx_spi_unprepare_transfer() local
414 if (is_polling(sdd)) in s3c64xx_spi_unprepare_transfer()
418 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_unprepare_transfer()
419 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_unprepare_transfer()
420 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_unprepare_transfer()
421 sdd->rx_dma.ch = NULL; in s3c64xx_spi_unprepare_transfer()
422 sdd->tx_dma.ch = NULL; in s3c64xx_spi_unprepare_transfer()
432 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_can_dma() local
434 if (sdd->rx_dma.ch && sdd->tx_dma.ch) in s3c64xx_spi_can_dma()
435 return xfer->len >= sdd->fifo_depth; in s3c64xx_spi_can_dma()
464 static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, in s3c64xx_iowrite_rep() argument
467 void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; in s3c64xx_iowrite_rep()
471 switch (sdd->cur_bpw) { in s3c64xx_iowrite_rep()
476 if (sdd->port_conf->use_32bit_io) in s3c64xx_iowrite_rep()
482 if (sdd->port_conf->use_32bit_io) in s3c64xx_iowrite_rep()
490 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_enable_datapath() argument
493 void __iomem *regs = sdd->regs; in s3c64xx_enable_datapath()
511 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
517 sdd->state |= TXBUSY; in s3c64xx_enable_datapath()
521 ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); in s3c64xx_enable_datapath()
523 s3c64xx_iowrite_rep(sdd, xfer); in s3c64xx_enable_datapath()
528 sdd->state |= RXBUSY; in s3c64xx_enable_datapath()
530 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL in s3c64xx_enable_datapath()
531 && !(sdd->cur_mode & SPI_CPHA)) in s3c64xx_enable_datapath()
537 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
540 ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg); in s3c64xx_enable_datapath()
553 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_spi_wait_for_timeout() argument
556 void __iomem *regs = sdd->regs; in s3c64xx_spi_wait_for_timeout()
559 u32 max_fifo = sdd->fifo_depth; in s3c64xx_spi_wait_for_timeout()
566 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); in s3c64xx_spi_wait_for_timeout()
569 return RX_FIFO_LVL(status, sdd); in s3c64xx_spi_wait_for_timeout()
572 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_wait_for_dma() argument
575 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_dma()
581 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_dma()
586 val = wait_for_completion_timeout(&sdd->xfer_completion, val); in s3c64xx_wait_for_dma()
600 while ((TX_FIFO_LVL(status, sdd) in s3c64xx_wait_for_dma()
601 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) in s3c64xx_wait_for_dma()
616 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, in s3c64xx_wait_for_pio() argument
619 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_pio()
629 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; in s3c64xx_wait_for_pio()
635 if (RX_FIFO_LVL(status, sdd) < xfer->len) in s3c64xx_wait_for_pio()
640 if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) in s3c64xx_wait_for_pio()
647 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); in s3c64xx_wait_for_pio()
654 sdd->state &= ~TXBUSY; in s3c64xx_wait_for_pio()
666 loops = xfer->len / sdd->fifo_depth; in s3c64xx_wait_for_pio()
670 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, in s3c64xx_wait_for_pio()
673 switch (sdd->cur_bpw) { in s3c64xx_wait_for_pio()
690 sdd->state &= ~RXBUSY; in s3c64xx_wait_for_pio()
695 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_config() argument
697 void __iomem *regs = sdd->regs; in s3c64xx_spi_config()
700 int div = sdd->port_conf->clk_div; in s3c64xx_spi_config()
703 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
715 if (sdd->cur_mode & SPI_CPOL) in s3c64xx_spi_config()
718 if (sdd->cur_mode & SPI_CPHA) in s3c64xx_spi_config()
728 switch (sdd->cur_bpw) { in s3c64xx_spi_config()
743 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) in s3c64xx_spi_config()
750 if (sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
751 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); in s3c64xx_spi_config()
754 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; in s3c64xx_spi_config()
759 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) in s3c64xx_spi_config()
777 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_prepare_message() local
784 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
786 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
802 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_transfer_one() local
803 const unsigned int fifo_len = sdd->fifo_depth; in s3c64xx_spi_transfer_one()
816 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
822 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { in s3c64xx_spi_transfer_one()
823 sdd->cur_bpw = bpw; in s3c64xx_spi_transfer_one()
824 sdd->cur_speed = speed; in s3c64xx_spi_transfer_one()
825 sdd->cur_mode = spi->mode; in s3c64xx_spi_transfer_one()
826 status = s3c64xx_spi_config(sdd); in s3c64xx_spi_transfer_one()
831 if (!is_polling(sdd) && xfer->len >= fifo_len && in s3c64xx_spi_transfer_one()
832 sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_transfer_one()
848 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
862 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); in s3c64xx_spi_transfer_one()
865 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); in s3c64xx_spi_transfer_one()
868 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_transfer_one()
870 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_transfer_one()
874 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
877 sdd->state &= ~RXBUSY; in s3c64xx_spi_transfer_one()
878 sdd->state &= ~TXBUSY; in s3c64xx_spi_transfer_one()
883 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); in s3c64xx_spi_transfer_one()
885 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
893 status = s3c64xx_wait_for_dma(sdd, xfer); in s3c64xx_spi_transfer_one()
895 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); in s3c64xx_spi_transfer_one()
901 (sdd->state & RXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
902 (sdd->state & TXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
908 if (xfer->tx_buf && (sdd->state & TXBUSY)) { in s3c64xx_spi_transfer_one()
909 dmaengine_pause(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
910 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
911 dmaengine_terminate_all(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
915 if (xfer->rx_buf && (sdd->state & RXBUSY)) { in s3c64xx_spi_transfer_one()
916 dmaengine_pause(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
917 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
918 dmaengine_terminate_all(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
923 s3c64xx_flush_fifo(sdd); in s3c64xx_spi_transfer_one()
989 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_setup() local
993 sdd = spi_controller_get_devdata(spi->controller); in s3c64xx_spi_setup()
1008 pm_runtime_get_sync(&sdd->pdev->dev); in s3c64xx_spi_setup()
1010 div = sdd->port_conf->clk_div; in s3c64xx_spi_setup()
1013 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_setup()
1017 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); in s3c64xx_spi_setup()
1022 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
1027 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1037 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); in s3c64xx_spi_setup()
1048 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
1054 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
1080 struct s3c64xx_spi_driver_data *sdd = data; in s3c64xx_spi_irq() local
1081 struct spi_controller *spi = sdd->host; in s3c64xx_spi_irq()
1084 val = readl(sdd->regs + S3C64XX_SPI_STATUS); in s3c64xx_spi_irq()
1104 complete(&sdd->xfer_completion); in s3c64xx_spi_irq()
1106 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_irq()
1108 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_irq()
1112 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
1113 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
1118 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_hwinit() argument
1120 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_hwinit()
1121 void __iomem *regs = sdd->regs; in s3c64xx_spi_hwinit()
1124 sdd->cur_speed = 0; in s3c64xx_spi_hwinit()
1127 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
1128 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_hwinit()
1129 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
1134 if (!sdd->port_conf->clk_from_cmu) in s3c64xx_spi_hwinit()
1155 s3c64xx_flush_fifo(sdd); in s3c64xx_spi_hwinit()
1205 struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_set_port_id() argument
1207 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; in s3c64xx_spi_set_port_id()
1218 sdd->port_id = ret; in s3c64xx_spi_set_port_id()
1223 sdd->port_id = pdev->id; in s3c64xx_spi_set_port_id()
1229 static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) in s3c64xx_spi_set_fifomask() argument
1231 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; in s3c64xx_spi_set_fifomask()
1234 sdd->rx_fifomask = port_conf->rx_fifomask; in s3c64xx_spi_set_fifomask()
1236 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << in s3c64xx_spi_set_fifomask()
1240 sdd->tx_fifomask = port_conf->tx_fifomask; in s3c64xx_spi_set_fifomask()
1242 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << in s3c64xx_spi_set_fifomask()
1249 struct s3c64xx_spi_driver_data *sdd; in s3c64xx_spi_probe() local
1269 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd)); in s3c64xx_spi_probe()
1275 sdd = spi_controller_get_devdata(host); in s3c64xx_spi_probe()
1276 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); in s3c64xx_spi_probe()
1277 sdd->host = host; in s3c64xx_spi_probe()
1278 sdd->cntrlr_info = sci; in s3c64xx_spi_probe()
1279 sdd->pdev = pdev; in s3c64xx_spi_probe()
1281 ret = s3c64xx_spi_set_port_id(pdev, sdd); in s3c64xx_spi_probe()
1285 if (sdd->port_conf->fifo_depth) in s3c64xx_spi_probe()
1286 sdd->fifo_depth = sdd->port_conf->fifo_depth; in s3c64xx_spi_probe()
1288 &sdd->fifo_depth)) in s3c64xx_spi_probe()
1289 sdd->fifo_depth = FIFO_DEPTH(sdd); in s3c64xx_spi_probe()
1291 s3c64xx_spi_set_fifomask(sdd); in s3c64xx_spi_probe()
1293 sdd->cur_bpw = 8; in s3c64xx_spi_probe()
1295 sdd->tx_dma.direction = DMA_MEM_TO_DEV; in s3c64xx_spi_probe()
1296 sdd->rx_dma.direction = DMA_DEV_TO_MEM; in s3c64xx_spi_probe()
1314 if (sdd->port_conf->has_loopback) in s3c64xx_spi_probe()
1317 if (!is_polling(sdd)) in s3c64xx_spi_probe()
1320 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); in s3c64xx_spi_probe()
1321 if (IS_ERR(sdd->regs)) in s3c64xx_spi_probe()
1322 return PTR_ERR(sdd->regs); in s3c64xx_spi_probe()
1323 sdd->sfr_start = mem_res->start; in s3c64xx_spi_probe()
1330 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi"); in s3c64xx_spi_probe()
1331 if (IS_ERR(sdd->clk)) in s3c64xx_spi_probe()
1332 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk), in s3c64xx_spi_probe()
1336 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name); in s3c64xx_spi_probe()
1337 if (IS_ERR(sdd->src_clk)) in s3c64xx_spi_probe()
1338 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), in s3c64xx_spi_probe()
1342 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_probe()
1343 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk"); in s3c64xx_spi_probe()
1344 if (IS_ERR(sdd->ioclk)) in s3c64xx_spi_probe()
1345 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk), in s3c64xx_spi_probe()
1356 s3c64xx_spi_hwinit(sdd); in s3c64xx_spi_probe()
1358 spin_lock_init(&sdd->lock); in s3c64xx_spi_probe()
1359 init_completion(&sdd->xfer_completion); in s3c64xx_spi_probe()
1362 "spi-s3c64xx", sdd); in s3c64xx_spi_probe()
1371 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_probe()
1382 mem_res, sdd->fifo_depth); in s3c64xx_spi_probe()
1399 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_remove() local
1403 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_remove()
1405 if (!is_polling(sdd)) { in s3c64xx_spi_remove()
1406 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_remove()
1407 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_remove()
1419 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_suspend() local
1430 sdd->cur_speed = 0; /* Output Clock is stopped */ in s3c64xx_spi_suspend()
1438 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_resume() local
1439 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_resume()
1457 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_runtime_suspend() local
1459 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_runtime_suspend()
1460 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1461 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_suspend()
1469 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); in s3c64xx_spi_runtime_resume() local
1472 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_runtime_resume()
1473 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1478 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1482 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_runtime_resume()
1486 s3c64xx_spi_hwinit(sdd); in s3c64xx_spi_runtime_resume()
1490 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_runtime_resume()
1495 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1497 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_resume()