drivers/spi/spi-pl022.c

3  * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
63  * Macros to access SSP Registers with their offsets
92  * SSP Control Register 0  - SSP_CR0
110  * SSP Control Register 0  - SSP_CR1
130  * SSP Status Register - SSP_SR
139  * SSP Clock Prescale Register  - SSP_CPSR
144  * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
152  * SSP Raw Interrupt Status Register - SSP_RIS
164  * SSP Masked Interrupt Status Register - SSP_MIS
176  * SSP Interrupt Clear Register - SSP_ICR
184  * SSP DMA Control Register - SSP_DMACR
192  * SSP Chip Select Control Register - SSP_CSR
198  * SSP Integration Test control Register - SSP_ITCR
204  * SSP Integration Test Input Register - SSP_ITIP
214  * SSP Integration Test output Register - SSP_ITOP
232  * SSP Test Data Register - SSP_TDR
249  * SSP State - Whether Enabled or Disabled
255  * SSP DMA State - Whether DMA Enabled or Disabled
261  * SSP Clock Defaults
267  * SSP Clock Parameter ranges
275  * SSP Interrupt related Macros
333  * struct pl022 - This is the private SSP driver data structure
336  * @phybase: the physical memory where the SSP device resides
337  * @virtbase: the virtual memory where the SSP is mapped
392  * struct chip_data - To maintain runtime state of SSP for each client chip
393  * @cr0: Value of control register CR0 of SSP - on later ST variants this
395  * @cr1: Value of control register CR1 of SSP
396  * @dmacr: Value of DMA control Register of SSP
404  * Runtime state of the SSP controller, maintained per chip,
421  * @pl022: SSP driver private data structure
449  * @pl022: SSP driver private data structure
468  * @pl022: SSP driver private data structure
486  * Default SSP Register Values
557  * load_ssp_default_config - Load default configuration for SSP
558  * @pl022: SSP driver private data structure
796  * @pl022: SSP driver's private data structure
1127  * pl022_interrupt_handler - Interrupt handler for SSP controller
1132  * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1165 		 * Disable and clear interrupts, disable SSP,
1266 	/* Enable SSP, turn on interrupts */
1306 	/* Flush FIFOs and enable SSP */
1362 	/* nothing more to do - disable spi/ssp and power off */
1557 		"SSP Target Frequency is: %u, Effective Frequency is %u\n",
1559 	dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1887 	 * Bus Number Which has been Assigned to this SSP controller
1929 		dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
1933 	/* Disable SSP */
2146 		 * an official ARM number), this is a PL022 SSP block
2171 		.name	= "ssp-pl022",
2192 MODULE_DESCRIPTION("PL022 SSP Controller Driver");