Lines Matching refs:tclk_hz

137 	u32 tclk_hz;
147 	tclk_hz = clk_get_rate(orion_spi->clk);
151 		 * Given the core_clk (tclk_hz) and the target rate (speed) we
161 		unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
211 		rate = DIV_ROUND_UP(tclk_hz, speed);
650 	unsigned long tclk_hz;
706 	tclk_hz = clk_get_rate(spi->clk);
718 				DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
721 			DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
724 	host->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);