drivers/spi/spi-mxs.c

59 	struct mxs_ssp		ssp;
68 	struct mxs_ssp *ssp = &spi->ssp;
77 		mxs_ssp_set_clk_rate(ssp, hz);
80 		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
91 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
97 	       ssp->base + HW_SSP_CTRL1(ssp));
99 	writel(0x0, ssp->base + HW_SSP_CMD0);
100 	writel(0x0, ssp->base + HW_SSP_CMD1);
128 	struct mxs_ssp *ssp = &spi->ssp;
132 		reg = readl_relaxed(ssp->base + offset);
155 	struct mxs_ssp *ssp = dev_id;
157 	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
159 		readl(ssp->base + HW_SSP_CTRL1(ssp)),
160 		readl(ssp->base + HW_SSP_STATUS(ssp)));
168 	struct mxs_ssp *ssp = &spi->ssp;
192 	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
212 		if (ssp->devid == IMX23_SSP) {
234 		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
241 		desc = dmaengine_prep_slave_sg(ssp->dmach,
243 				(ssp->devid == IMX23_SSP) ? 1 : 4,
247 			dev_err(ssp->dev,
253 		desc = dmaengine_prep_slave_sg(ssp->dmach,
259 			dev_err(ssp->dev,
275 	dma_async_issue_pending(ssp->dmach);
279 		dev_err(ssp->dev, "DMA transfer timeout\n");
281 		dmaengine_terminate_all(ssp->dmach);
290 		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
303 	struct mxs_ssp *ssp = &spi->ssp;
306 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
311 			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
313 		if (ssp->devid == IMX23_SSP) {
315 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
317 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
319 			writel(1, ssp->base + HW_SSP_XFER_SIZE);
324 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
327 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
330 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
336 			writel(*buf, ssp->base + HW_SSP_DATA(ssp));
339 			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
342 			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
346 			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
365 	struct mxs_ssp *ssp = &spi->ssp;
372 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
374 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
384 		t->effective_speed_hz = ssp->clk_rate;
401 				ssp->base + HW_SSP_CTRL1(ssp) +
414 				ssp->base + HW_SSP_CTRL1(ssp) +
430 			stmp_reset_block(ssp->base);
447 	struct mxs_ssp *ssp = &spi->ssp;
450 	clk_disable_unprepare(ssp->clk);
454 		int ret2 = clk_prepare_enable(ssp->clk);
468 	struct mxs_ssp *ssp = &spi->ssp;
475 	ret = clk_prepare_enable(ssp->clk);
535 	struct mxs_ssp *ssp;
581 	ssp = &spi->ssp;
582 	ssp->dev = &pdev->dev;
583 	ssp->clk = clk;
584 	ssp->base = base;
585 	ssp->devid = devid;
590 			       dev_name(&pdev->dev), ssp);
594 	ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
595 	if (IS_ERR(ssp->dmach)) {
596 		dev_err(ssp->dev, "Failed to request DMA\n");
597 		ret = PTR_ERR(ssp->dmach);
601 	pm_runtime_enable(ssp->dev);
602 	if (!pm_runtime_enabled(ssp->dev)) {
603 		ret = mxs_spi_runtime_resume(ssp->dev);
605 			dev_err(ssp->dev, "runtime resume failed\n");
610 	ret = pm_runtime_resume_and_get(ssp->dev);
612 		dev_err(ssp->dev, "runtime_get_sync failed\n");
616 	clk_set_rate(ssp->clk, clk_freq);
618 	ret = stmp_reset_block(ssp->base);
628 	pm_runtime_put(ssp->dev);
633 	pm_runtime_put(ssp->dev);
635 	pm_runtime_disable(ssp->dev);
637 	dma_release_channel(ssp->dmach);
647 	struct mxs_ssp *ssp;
651 	ssp = &spi->ssp;
657 	dma_release_channel(ssp->dmach);