Lines Matching defs:q
277 static inline int needs_swap_endian(struct fsl_qspi *q)
279 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
282 static inline int needs_4x_clock(struct fsl_qspi *q)
284 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
287 static inline int needs_fill_txfifo(struct fsl_qspi *q)
289 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
292 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
294 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
297 static inline int needs_amba_base_offset(struct fsl_qspi *q)
299 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
302 static inline int needs_tdh_setting(struct fsl_qspi *q)
304 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
311 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
313 return needs_swap_endian(q) ? __swab32(a) : a;
323 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
325 if (q->devtype_data->little_endian)
331 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
333 if (q->devtype_data->little_endian)
341 struct fsl_qspi *q = dev_id;
345 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
346 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
349 complete(&q->c);
351 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);
355 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)
370 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
373 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);
376 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);
379 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);
382 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);
403 (op->data.nbytes > q->devtype_data->ahb_buf_size ||
404 (op->data.nbytes > q->devtype_data->rxfifo - 4 &&
409 op->data.nbytes > q->devtype_data->txfifo)
415 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
418 void __iomem *base = q->iobase;
459 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
460 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
464 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
467 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
468 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
471 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
475 ret = clk_prepare_enable(q->clk_en);
479 ret = clk_prepare_enable(q->clk);
481 clk_disable_unprepare(q->clk_en);
485 if (needs_wakeup_wait_mode(q))
486 cpu_latency_qos_add_request(&q->pm_qos_req, 0);
491 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
493 if (needs_wakeup_wait_mode(q))
494 cpu_latency_qos_remove_request(&q->pm_qos_req);
496 clk_disable_unprepare(q->clk);
497 clk_disable_unprepare(q->clk_en);
507 static void fsl_qspi_invalidate(struct fsl_qspi *q)
511 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
513 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
522 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
525 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
531 if (q->selected == spi_get_chipselect(spi, 0))
534 if (needs_4x_clock(q))
537 fsl_qspi_clk_disable_unprep(q);
539 ret = clk_set_rate(q->clk, rate);
543 ret = fsl_qspi_clk_prep_enable(q);
547 q->selected = spi_get_chipselect(spi, 0);
549 fsl_qspi_invalidate(q);
552 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
555 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
559 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
562 void __iomem *base = q->iobase;
568 val = fsl_qspi_endian_xchg(q, val);
569 qspi_writel(q, val, base + QUADSPI_TBDR);
574 val = fsl_qspi_endian_xchg(q, val);
575 qspi_writel(q, val, base + QUADSPI_TBDR);
578 if (needs_fill_txfifo(q)) {
580 qspi_writel(q, 0, base + QUADSPI_TBDR);
584 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,
587 void __iomem *base = q->iobase;
593 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
594 val = fsl_qspi_endian_xchg(q, val);
599 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
600 val = fsl_qspi_endian_xchg(q, val);
605 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)
607 void __iomem *base = q->iobase;
610 init_completion(&q->c);
617 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),
621 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))
625 fsl_qspi_read_rxfifo(q, op);
630 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
635 if (!q->devtype_data->little_endian)
644 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
645 void __iomem *base = q->iobase;
648 int invalid_mstrid = q->devtype_data->invalid_mstrid;
650 mutex_lock(&q->lock);
653 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
656 fsl_qspi_select_mem(q, mem->spi, op);
658 if (needs_amba_base_offset(q))
659 addr_offset = q->memmap_phy;
661 qspi_writel(q,
662 q->selected * q->devtype_data->ahb_buf_size + addr_offset,
665 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
669 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
672 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
673 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
674 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
676 fsl_qspi_prepare_lut(q, op);
683 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
685 fsl_qspi_read_ahb(q, op);
687 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
691 fsl_qspi_fill_txfifo(q, op);
693 err = fsl_qspi_do_op(q, op);
697 fsl_qspi_invalidate(q);
699 mutex_unlock(&q->lock);
706 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
709 if (op->data.nbytes > q->devtype_data->txfifo)
710 op->data.nbytes = q->devtype_data->txfifo;
712 if (op->data.nbytes > q->devtype_data->ahb_buf_size)
713 op->data.nbytes = q->devtype_data->ahb_buf_size;
714 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))
721 static int fsl_qspi_default_setup(struct fsl_qspi *q)
723 void __iomem *base = q->iobase;
728 fsl_qspi_clk_disable_unprep(q);
731 ret = clk_set_rate(q->clk, 66000000);
735 ret = fsl_qspi_clk_prep_enable(q);
740 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
745 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
753 if (needs_tdh_setting(q))
754 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
758 reg = qspi_readl(q, base + QUADSPI_SMPR);
759 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
765 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
766 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
767 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
769 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
770 q->iobase + QUADSPI_BFGENCR);
771 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
772 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
773 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
776 if (needs_amba_base_offset(q))
777 addr_offset = q->memmap_phy;
786 qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
788 qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
790 qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
792 qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
795 q->selected = -1;
798 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
802 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
805 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
812 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);
821 if (of_get_available_child_count(q->dev->of_node) == 1)
822 return dev_name(q->dev);
825 "%s-%d", dev_name(q->dev),
849 struct fsl_qspi *q = data;
852 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
853 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
858 struct fsl_qspi *q = data;
860 fsl_qspi_clk_disable_unprep(q);
862 mutex_destroy(&q->lock);
871 struct fsl_qspi *q;
874 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*q));
881 q = spi_controller_get_devdata(ctlr);
882 q->dev = dev;
883 q->devtype_data = of_device_get_match_data(dev);
884 if (!q->devtype_data)
887 platform_set_drvdata(pdev, q);
890 q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI");
891 if (IS_ERR(q->iobase))
892 return PTR_ERR(q->iobase);
898 q->memmap_phy = res->start;
900 q->ahb_addr = devm_ioremap(dev, q->memmap_phy,
901 (q->devtype_data->ahb_buf_size * 4));
902 if (!q->ahb_addr)
906 q->clk_en = devm_clk_get(dev, "qspi_en");
907 if (IS_ERR(q->clk_en))
908 return PTR_ERR(q->clk_en);
910 q->clk = devm_clk_get(dev, "qspi");
911 if (IS_ERR(q->clk))
912 return PTR_ERR(q->clk);
914 mutex_init(&q->lock);
916 ret = fsl_qspi_clk_prep_enable(q);
922 ret = devm_add_action_or_reset(dev, fsl_qspi_cleanup, q);
932 fsl_qspi_irq_handler, 0, pdev->name, q);
943 fsl_qspi_default_setup(q);
947 ret = devm_add_action_or_reset(dev, fsl_qspi_disable, q);
965 struct fsl_qspi *q = dev_get_drvdata(dev);
967 fsl_qspi_default_setup(q);