Lines Matching refs:clk_reg
432 u32 clk_reg;
448 clk_reg = readl(cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG);
450 if (FIELD_GET(MRVL_XSPI_CLK_DIV, clk_reg) != i) {
451 clk_reg &= ~MRVL_XSPI_CLK_ENABLE;
452 writel(clk_reg,
454 clk_reg = FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
455 clk_reg &= ~MRVL_XSPI_CLK_DIV;
456 clk_reg |= FIELD_PREP(MRVL_XSPI_CLK_DIV, i);
457 clk_reg |= MRVL_XSPI_CLK_ENABLE;
458 clk_reg |= MRVL_XSPI_IRQ_ENABLE;
463 writel(clk_reg,