Lines Matching refs:hw
52 void (*rx_word)(struct au1550_spi *hw);
53 void (*tx_word)(struct au1550_spi *hw);
55 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
89 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
101 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
103 u32 mainclk_hz = hw->pdata->mainclk_hz;
124 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
126 hw->regs->psc_spimsk =
132 hw->regs->psc_spievent =
139 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
143 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
146 pcr = hw->regs->psc_spipcr;
162 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
168 if (hw->pdata->deactivate_cs)
169 hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0),
174 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
176 cfg = hw->regs->psc_spicfg;
178 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
195 if (hw->usedma && spi->bits_per_word <= 8)
204 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
206 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
209 stat = hw->regs->psc_spistat;
213 if (hw->pdata->activate_cs)
214 hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0),
222 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
237 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
239 cfg = hw->regs->psc_spicfg;
241 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
244 if (hw->usedma && bpw <= 8)
253 cfg |= au1550_spi_baudcfg(hw, hz);
255 hw->regs->psc_spicfg = cfg;
260 stat = hw->regs->psc_spistat;
265 au1550_spi_reset_fifos(hw);
266 au1550_spi_mask_ack_all(hw);
278 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
280 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
281 if (!hw->dma_rx_tmpbuf)
283 hw->dma_rx_tmpbuf_size = size;
284 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
286 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
287 kfree(hw->dma_rx_tmpbuf);
288 hw->dma_rx_tmpbuf = 0;
289 hw->dma_rx_tmpbuf_size = 0;
295 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
297 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
298 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
299 kfree(hw->dma_rx_tmpbuf);
300 hw->dma_rx_tmpbuf = 0;
301 hw->dma_rx_tmpbuf_size = 0;
306 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
311 hw->len = t->len;
312 hw->tx_count = 0;
313 hw->rx_count = 0;
315 hw->tx = t->tx_buf;
316 hw->rx = t->rx_buf;
326 dma_tx_addr = dma_map_single(hw->dev, (void *)t->tx_buf,
328 if (dma_mapping_error(hw->dev, dma_tx_addr))
329 dev_err(hw->dev, "tx dma map error\n");
333 dma_rx_addr = dma_map_single(hw->dev, (void *)t->rx_buf,
335 if (dma_mapping_error(hw->dev, dma_rx_addr))
336 dev_err(hw->dev, "rx dma map error\n");
338 if (t->len > hw->dma_rx_tmpbuf_size) {
341 au1550_spi_dma_rxtmp_free(hw);
342 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
347 hw->rx = hw->dma_rx_tmpbuf;
348 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
349 dma_sync_single_for_device(hw->dev, dma_rx_addr,
354 dma_sync_single_for_device(hw->dev, dma_rx_addr,
356 hw->tx = hw->rx;
360 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
363 dev_err(hw->dev, "rx dma put dest error\n");
365 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
368 dev_err(hw->dev, "tx dma put source error\n");
370 au1xxx_dbdma_start(hw->dma_rx_ch);
371 au1xxx_dbdma_start(hw->dma_tx_ch);
374 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
378 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
381 wait_for_completion(&hw->host_done);
383 au1xxx_dbdma_stop(hw->dma_tx_ch);
384 au1xxx_dbdma_stop(hw->dma_rx_ch);
388 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
393 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
396 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
399 return min(hw->rx_count, hw->tx_count);
402 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
406 stat = hw->regs->psc_spistat;
407 evnt = hw->regs->psc_spievent;
410 dev_err(hw->dev, "Unexpected IRQ!\n");
423 au1550_spi_mask_ack_all(hw);
424 au1xxx_dbdma_stop(hw->dma_rx_ch);
425 au1xxx_dbdma_stop(hw->dma_tx_ch);
428 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
429 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
431 au1xxx_dbdma_reset(hw->dma_rx_ch);
432 au1xxx_dbdma_reset(hw->dma_tx_ch);
433 au1550_spi_reset_fifos(hw);
436 dev_err(hw->dev,
439 dev_err(hw->dev,
443 complete(&hw->host_done);
449 au1550_spi_mask_ack_all(hw);
450 hw->rx_count = hw->len;
451 hw->tx_count = hw->len;
452 complete(&hw->host_done);
460 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
462 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
464 if (hw->rx) { \
465 *(u##size *)hw->rx = (u##size)fifoword; \
466 hw->rx += (size) / 8; \
468 hw->rx_count += (size) / 8; \
472 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
475 if (hw->tx) { \
476 fifoword = *(u##size *)hw->tx & (u32)(mask); \
477 hw->tx += (size) / 8; \
479 hw->tx_count += (size) / 8; \
480 if (hw->tx_count >= hw->len) \
482 hw->regs->psc_spitxrx = fifoword; \
496 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
498 hw->tx = t->tx_buf;
499 hw->rx = t->rx_buf;
500 hw->len = t->len;
501 hw->tx_count = 0;
502 hw->rx_count = 0;
508 while (hw->tx_count < hw->len) {
510 hw->tx_word(hw);
512 if (hw->tx_count >= hw->len) {
517 stat = hw->regs->psc_spistat;
524 hw->regs->psc_spimsk = mask;
528 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
531 wait_for_completion(&hw->host_done);
533 return min(hw->rx_count, hw->tx_count);
536 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
541 stat = hw->regs->psc_spistat;
542 evnt = hw->regs->psc_spievent;
545 dev_err(hw->dev, "Unexpected IRQ!\n");
557 au1550_spi_mask_ack_all(hw);
558 au1550_spi_reset_fifos(hw);
559 dev_err(hw->dev,
562 complete(&hw->host_done);
572 stat = hw->regs->psc_spistat;
584 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
585 hw->rx_word(hw);
588 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
589 hw->tx_word(hw);
593 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
612 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
614 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
618 if (hw->rx_count >= hw->len) {
620 au1550_spi_mask_ack_all(hw);
621 complete(&hw->host_done);
628 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
630 return hw->txrx_bufs(spi, t);
635 struct au1550_spi *hw = dev;
637 return hw->irq_callback(hw);
640 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
643 if (hw->usedma) {
644 hw->txrx_bufs = &au1550_spi_dma_txrxb;
645 hw->irq_callback = &au1550_spi_dma_irq_callback;
647 hw->rx_word = &au1550_spi_rx_word_8;
648 hw->tx_word = &au1550_spi_tx_word_8;
649 hw->txrx_bufs = &au1550_spi_pio_txrxb;
650 hw->irq_callback = &au1550_spi_pio_irq_callback;
653 hw->rx_word = &au1550_spi_rx_word_16;
654 hw->tx_word = &au1550_spi_tx_word_16;
655 hw->txrx_bufs = &au1550_spi_pio_txrxb;
656 hw->irq_callback = &au1550_spi_pio_irq_callback;
658 hw->rx_word = &au1550_spi_rx_word_32;
659 hw->tx_word = &au1550_spi_tx_word_32;
660 hw->txrx_bufs = &au1550_spi_pio_txrxb;
661 hw->irq_callback = &au1550_spi_pio_irq_callback;
665 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
670 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
672 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
675 hw->regs->psc_spicfg = 0;
678 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
682 stat = hw->regs->psc_spistat;
687 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
697 hw->regs->psc_spicfg = cfg;
700 au1550_spi_mask_ack_all(hw);
702 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
706 stat = hw->regs->psc_spistat;
710 au1550_spi_reset_fifos(hw);
716 struct au1550_spi *hw;
732 hw = spi_controller_get_devdata(host);
734 hw->host = host;
735 hw->pdata = dev_get_platdata(&pdev->dev);
736 hw->dev = &pdev->dev;
738 if (hw->pdata == NULL) {
750 hw->irq = r->start;
752 hw->usedma = 0;
755 hw->dma_tx_id = r->start;
758 hw->dma_rx_id = r->start;
763 hw->usedma = 1;
775 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
777 if (!hw->ioarea) {
783 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
784 if (!hw->regs) {
790 platform_set_drvdata(pdev, hw);
792 init_completion(&hw->host_done);
794 hw->bitbang.ctlr = hw->host;
795 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
796 hw->bitbang.chipselect = au1550_spi_chipsel;
797 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
799 if (hw->usedma) {
800 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
801 hw->dma_tx_id, NULL, (void *)hw);
802 if (hw->dma_tx_ch == 0) {
808 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
809 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
818 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
819 ddma_memid, NULL, (void *)hw);
820 if (hw->dma_rx_ch == 0) {
826 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
827 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
835 err = au1550_spi_dma_rxtmp_alloc(hw,
844 au1550_spi_bits_handlers_set(hw, 8);
846 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
853 host->num_chipselect = hw->pdata->num_chipselect;
868 host->max_speed_hz = hw->pdata->mainclk_hz / min_div;
870 hw->pdata->mainclk_hz / (max_div + 1) + 1;
873 au1550_spi_setup_psc_as_spi(hw);
875 err = spi_bitbang_start(&hw->bitbang);
888 free_irq(hw->irq, hw);
891 au1550_spi_dma_rxtmp_free(hw);
895 if (hw->usedma)
896 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
900 if (hw->usedma)
901 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
904 iounmap((void __iomem *)hw->regs);
911 spi_controller_put(hw->host);
919 struct au1550_spi *hw = platform_get_drvdata(pdev);
922 hw->host->bus_num);
924 spi_bitbang_stop(&hw->bitbang);
925 free_irq(hw->irq, hw);
926 iounmap((void __iomem *)hw->regs);
927 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
929 if (hw->usedma) {
930 au1550_spi_dma_rxtmp_free(hw);
931 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
932 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
935 spi_controller_put(hw->host);