drivers/spi/spi-airoha-snfi.c

223 static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
229 	err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
235 	err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
242 	err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
247 	return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
253 static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
255 	return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
258 static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
268 		err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
276 		err = regmap_write(as_ctrl->regmap_ctrl,
283 		err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
294 static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
304 		err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
312 		err = regmap_read(as_ctrl->regmap_ctrl,
319 		err = regmap_write(as_ctrl->regmap_ctrl,
328 static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
337 		err = regmap_write(as_ctrl->regmap_ctrl,
342 		err = regmap_write(as_ctrl->regmap_ctrl,
347 		err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
354 		err = regmap_write(as_ctrl->regmap_ctrl,
359 		err = regmap_write(as_ctrl->regmap_ctrl,
366 		err = regmap_write(as_ctrl->regmap_ctrl,
372 		err = regmap_write(as_ctrl->regmap_ctrl,
377 		err = regmap_write(as_ctrl->regmap_ctrl,
387 	return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
390 static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
399 		err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
403 		err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
412 static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
421 		err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
425 		err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
434 static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
439 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
445 	return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
449 static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
454 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
460 	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
466 	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
472 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
478 	switch (as_ctrl->nfi_cfg.spare_size) {
493 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
498 	switch (as_ctrl->nfi_cfg.page_size) {
510 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
516 	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
517 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
523 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
529 	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
530 	return regmap_update_bits(as_ctrl->regmap_nfi,
573 		struct airoha_snand_ctrl *as_ctrl;
575 		as_ctrl = spi_controller_get_devdata(mem->spi->controller);
576 		max_len = as_ctrl->nfi_cfg.sec_size;
577 		max_len += as_ctrl->nfi_cfg.spare_size;
578 		max_len *= as_ctrl->nfi_cfg.sec_num;
632 	struct airoha_snand_ctrl *as_ctrl;
650 	as_ctrl = spi_controller_get_devdata(spi->controller);
651 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
655 	err = airoha_snand_nfi_config(as_ctrl);
659 	dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
661 	err = dma_mapping_error(as_ctrl->dev, dma_addr);
666 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
672 	val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
674 	err = regmap_update_bits(as_ctrl->regmap_nfi,
681 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
687 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
693 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
698 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
704 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
709 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
714 	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
719 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
724 	err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
735 	err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
741 	err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
750 	dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
752 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
761 	dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
772 	struct airoha_snand_ctrl *as_ctrl;
777 	as_ctrl = spi_controller_get_devdata(spi->controller);
778 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
783 	dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
785 	err = dma_mapping_error(as_ctrl->dev, dma_addr);
789 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
793 	err = airoha_snand_nfi_config(as_ctrl);
803 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
809 			 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
810 	err = regmap_update_bits(as_ctrl->regmap_nfi,
816 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
822 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
827 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
831 	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
836 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
842 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
847 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
851 	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
856 	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
861 	err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
867 	err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
878 	err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
884 	dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
886 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
893 	dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
902 	struct airoha_snand_ctrl *as_ctrl;
905 	as_ctrl = spi_controller_get_devdata(mem->spi->controller);
908 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
912 	err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
917 	err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
927 		err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
936 		err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
944 		err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
949 		err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
955 	return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
969 	struct airoha_snand_ctrl *as_ctrl;
973 	as_ctrl = spi_controller_get_devdata(spi->controller);
974 	txrx_buf = devm_kzalloc(as_ctrl->dev, SPI_NAND_CACHE_SIZE,
984 static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
989 	err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
995 	err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
1002 	as_ctrl->nfi_cfg.sec_size = sec_size;
1003 	as_ctrl->nfi_cfg.sec_num = sec_num;
1004 	as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
1005 	as_ctrl->nfi_cfg.spare_size = 16;
1007 	err = airoha_snand_nfi_init(as_ctrl);
1011 	return airoha_snand_nfi_config(as_ctrl);
1038 	struct airoha_snand_ctrl *as_ctrl;
1044 	ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
1048 	as_ctrl = spi_controller_get_devdata(ctrl);
1049 	as_ctrl->dev = dev;
1055 	as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
1057 	if (IS_ERR(as_ctrl->regmap_ctrl))
1058 		return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
1065 	as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
1067 	if (IS_ERR(as_ctrl->regmap_nfi))
1068 		return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
1071 	as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
1072 	if (IS_ERR(as_ctrl->spi_clk))
1073 		return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
1076 	err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
1087 	err = airoha_snand_nfi_setup(as_ctrl);