Lines Matching refs:ctrl
220 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
221 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
331 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_ahb_reg_read() argument
334 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
351 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_ahb_reg_write() argument
354 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
371 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_read() argument
374 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
378 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_write() argument
381 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
403 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_rd_fifo_avail() argument
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
422 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
429 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_avail() argument
436 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
441 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
447 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
448 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
455 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_wr_fifo_done() argument
461 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
467 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
481 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, in qcom_swrm_cmd_fifo_wr_cmd() argument
494 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
498 if (swrm_wait_for_wr_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_wr_cmd()
502 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
505 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
507 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
511 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_cmd_fifo_wr_cmd()
516 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
529 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_cmd_fifo_rd_cmd() argument
535 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
541 swrm_wait_for_wr_fifo_avail(ctrl); in qcom_swrm_cmd_fifo_rd_cmd()
545 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
549 if (swrm_wait_for_rd_fifo_avail(ctrl)) in qcom_swrm_cmd_fifo_rd_cmd()
553 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
558 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
562 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
564 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
565 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
575 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
577 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
582 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_alert_slave_dev_num() argument
587 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
593 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
601 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_device_status() argument
606 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
607 ctrl->slave_status = val; in qcom_swrm_get_device_status()
614 ctrl->status[i] = s; in qcom_swrm_get_device_status()
621 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_set_slave_dev_num() local
624 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
639 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_enumerate() local
650 if (!ctrl->status[i]) in qcom_swrm_enumerate()
654 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
657 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
668 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
674 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
687 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
693 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_wake_irq_handler() local
696 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
698 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
701 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
705 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
706 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
707 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
710 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
711 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
718 struct qcom_swrm_ctrl *ctrl = dev_id; in qcom_swrm_irq_handler() local
723 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
725 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
727 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
737 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); in qcom_swrm_irq_handler()
739 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
742 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
748 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
749 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
750 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
751 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
754 qcom_swrm_get_device_status(ctrl); in qcom_swrm_irq_handler()
755 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
756 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
760 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
763 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
764 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
765 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
766 ctrl->intr_mask); in qcom_swrm_irq_handler()
769 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
770 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
772 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
777 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
778 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
780 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
785 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
786 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
788 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
791 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
794 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
795 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
797 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
800 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
803 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
806 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
807 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
808 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
809 ctrl->intr_mask); in qcom_swrm_irq_handler()
812 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
815 ctrl->intr_mask &= in qcom_swrm_irq_handler()
817 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
818 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
819 ctrl->intr_mask); in qcom_swrm_irq_handler()
822 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
831 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
832 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
834 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
842 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
849 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
851 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
853 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
856 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
860 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) in swrm_wait_for_frame_gen_enabled() argument
866 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], in swrm_wait_for_frame_gen_enabled()
874 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
880 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_init() argument
885 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
886 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
888 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
890 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
893 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
895 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
897 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
898 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
902 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
904 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
906 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
907 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
908 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
910 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
911 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
912 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
915 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
919 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
920 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
924 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
929 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
932 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
935 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
939 if (ctrl->mmio) { in qcom_swrm_init()
940 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
945 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
949 swrm_wait_for_frame_gen_enabled(ctrl); in qcom_swrm_init()
950 ctrl->slave_status = 0; in qcom_swrm_init()
951 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
953 if (ctrl->version >= SWRM_VERSION_3_1_0) in qcom_swrm_init()
954 ctrl->wr_fifo_depth = FIELD_GET(SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
956 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
963 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_read_prop() local
965 if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_read_prop()
976 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_xfer_msg() local
983 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
993 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
1007 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_pre_bank_switch() local
1010 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
1012 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
1013 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
1015 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
1022 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_params() local
1023 u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1]; in qcom_swrm_port_params()
1025 return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num), in qcom_swrm_port_params()
1033 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_transport_params() local
1036 int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK]; in qcom_swrm_transport_params()
1041 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
1047 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1052 offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]; in qcom_swrm_transport_params()
1056 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1062 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]; in qcom_swrm_transport_params()
1066 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1072 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]; in qcom_swrm_transport_params()
1077 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1082 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK]; in qcom_swrm_transport_params()
1087 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1090 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1097 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]; in qcom_swrm_transport_params()
1099 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1111 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_port_enable() local
1113 u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK]; in qcom_swrm_port_enable()
1117 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1124 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1141 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); in qcom_swrm_compute_params() local
1152 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1169 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1171 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1202 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_free_ports() argument
1209 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1212 port_mask = &ctrl->port_mask; in qcom_swrm_stream_free_ports()
1217 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1220 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_stream_alloc_ports() argument
1234 ctrl->nports); in qcom_swrm_stream_alloc_ports()
1249 guard(mutex)(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1258 if (ctrl->bus.id != m_rt->bus->id) in qcom_swrm_stream_alloc_ports()
1261 port_mask = &ctrl->port_mask; in qcom_swrm_stream_alloc_ports()
1262 maxport = ctrl->nports; in qcom_swrm_stream_alloc_ports()
1275 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1286 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1296 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params() local
1297 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1300 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, in qcom_swrm_hw_params()
1303 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_params()
1311 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free() local
1312 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1314 qcom_swrm_stream_free_ports(ctrl, sruntime); in qcom_swrm_hw_free()
1315 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1323 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream() local
1325 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1332 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream() local
1334 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1340 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup() local
1343 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1345 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1348 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1358 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown() local
1360 swrm_wait_for_wr_fifo_done(ctrl); in qcom_swrm_shutdown()
1361 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1362 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1379 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_register_dais() argument
1381 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1384 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1397 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1411 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1416 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) in qcom_swrm_get_port_config() argument
1418 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1422 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1424 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1425 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1429 if (val != ctrl->num_din_ports) { in qcom_swrm_get_port_config()
1430 dev_err(ctrl->dev, "din-ports (%d) mismatch with controller (%d)", in qcom_swrm_get_port_config()
1431 val, ctrl->num_din_ports); in qcom_swrm_get_port_config()
1434 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1439 if (val != ctrl->num_dout_ports) { in qcom_swrm_get_port_config()
1440 dev_err(ctrl->dev, "dout-ports (%d) mismatch with controller (%d)", in qcom_swrm_get_port_config()
1441 val, ctrl->num_dout_ports); in qcom_swrm_get_port_config()
1444 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1447 ctrl->nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1449 ctrl->pconfig = devm_kcalloc(ctrl->dev, ctrl->nports + 1, in qcom_swrm_get_port_config()
1450 sizeof(*ctrl->pconfig), GFP_KERNEL); in qcom_swrm_get_port_config()
1451 if (!ctrl->pconfig) in qcom_swrm_get_port_config()
1454 set_bit(0, &ctrl->port_mask); in qcom_swrm_get_port_config()
1456 for (i = 0; i < ctrl->nports; i++) { in qcom_swrm_get_port_config()
1457 pcfg = &ctrl->pconfig[i + 1]; in qcom_swrm_get_port_config()
1477 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1508 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show() local
1511 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1513 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1516 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1520 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1521 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1524 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1525 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1538 struct qcom_swrm_ctrl *ctrl; local
1543 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1544 if (!ctrl)
1548 ctrl->max_reg = data->max_reg;
1549 ctrl->reg_layout = data->reg_layout;
1550 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1551 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1557 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1558 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1559 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1560 if (!ctrl->regmap)
1563 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1564 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1565 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1566 if (IS_ERR(ctrl->mmio))
1567 return PTR_ERR(ctrl->mmio);
1571 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1572 if (IS_ERR(ctrl->audio_cgcr)) {
1574 ret = PTR_ERR(ctrl->audio_cgcr);
1579 ctrl->irq = of_irq_get(dev->of_node, 0);
1580 if (ctrl->irq < 0) {
1581 ret = ctrl->irq;
1585 ctrl->hclk = devm_clk_get(dev, "iface");
1586 if (IS_ERR(ctrl->hclk)) {
1587 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1591 clk_prepare_enable(ctrl->hclk);
1593 ctrl->dev = dev;
1594 dev_set_drvdata(&pdev->dev, ctrl);
1595 mutex_init(&ctrl->port_lock);
1596 init_completion(&ctrl->broadcast);
1597 init_completion(&ctrl->enumeration);
1599 ctrl->bus.ops = &qcom_swrm_ops;
1600 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1601 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1602 ctrl->bus.clk_stop_timeout = 300;
1604 ret = qcom_swrm_get_port_config(ctrl);
1608 params = &ctrl->bus.params;
1613 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1617 prop = &ctrl->bus.prop;
1625 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1627 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1631 "soundwire", ctrl);
1637 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1638 if (ctrl->wake_irq > 0) {
1639 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1642 "swr_wake_irq", ctrl);
1649 ctrl->bus.controller_id = -1;
1651 if (ctrl->version > SWRM_VERSION_1_3_0) {
1652 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1653 ctrl->bus.controller_id = val;
1656 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1663 qcom_swrm_init(ctrl);
1664 wait_for_completion_timeout(&ctrl->enumeration,
1666 ret = qcom_swrm_register_dais(ctrl);
1671 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1672 ctrl->version & 0xffff);
1681 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1682 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1689 sdw_bus_master_delete(&ctrl->bus);
1691 clk_disable_unprepare(ctrl->hclk);
1698 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); local
1700 sdw_bus_master_delete(&ctrl->bus);
1701 clk_disable_unprepare(ctrl->hclk);
1706 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1709 if (ctrl->wake_irq > 0) {
1710 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1711 disable_irq_nosync(ctrl->wake_irq);
1714 clk_prepare_enable(ctrl->hclk);
1716 if (ctrl->clock_stop_not_supported) {
1717 reinit_completion(&ctrl->enumeration);
1718 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1721 qcom_swrm_init(ctrl);
1724 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1725 dev_err(ctrl->dev, "link failed to connect\n");
1728 wait_for_completion_timeout(&ctrl->enumeration,
1730 qcom_swrm_get_device_status(ctrl);
1731 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1733 reset_control_reset(ctrl->audio_cgcr);
1735 if (ctrl->version == SWRM_VERSION_1_7_0) {
1736 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1737 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1739 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1740 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1741 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1744 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1746 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1749 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1750 if (ctrl->version < SWRM_VERSION_2_0_0)
1751 ctrl->reg_write(ctrl,
1752 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1753 ctrl->intr_mask);
1754 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1755 ctrl->intr_mask);
1758 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1759 dev_err(ctrl->dev, "link failed to connect\n");
1761 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1763 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1771 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); local
1774 swrm_wait_for_wr_fifo_done(ctrl);
1775 if (!ctrl->clock_stop_not_supported) {
1777 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1778 if (ctrl->version < SWRM_VERSION_2_0_0)
1779 ctrl->reg_write(ctrl,
1780 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1781 ctrl->intr_mask);
1782 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1783 ctrl->intr_mask);
1785 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1791 ret = sdw_bus_clk_stop(&ctrl->bus);
1798 clk_disable_unprepare(ctrl->hclk);
1802 if (ctrl->wake_irq > 0) {
1803 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1804 enable_irq(ctrl->wake_irq);