289 u32 geni_se_get_qup_hw_version(struct geni_se *se)  in geni_se_get_qup_hw_version()  argument
291 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_get_qup_hw_version()
330 static void geni_se_irq_clear(struct geni_se *se)  in geni_se_irq_clear()  argument
332 	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);  in geni_se_irq_clear()
333 	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_se_irq_clear()
334 	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);  in geni_se_irq_clear()
335 	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);  in geni_se_irq_clear()
336 	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);  in geni_se_irq_clear()
337 	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);  in geni_se_irq_clear()
349 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)  in geni_se_init()  argument
353 	geni_se_irq_clear(se);  in geni_se_init()
354 	geni_se_io_init(se->base);  in geni_se_init()
355 	geni_se_io_set_mode(se->base);  in geni_se_init()
357 	writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);  in geni_se_init()
358 	writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);  in geni_se_init()
360 	val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);  in geni_se_init()
362 	writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_init()
364 	val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);  in geni_se_init()
366 	writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_init()
370 static void geni_se_select_fifo_mode(struct geni_se *se)  in geni_se_select_fifo_mode()  argument
372 	u32 proto = geni_se_read_proto(se);  in geni_se_select_fifo_mode()
375 	geni_se_irq_clear(se);  in geni_se_select_fifo_mode()
380 		val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_fifo_mode()
384 			writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_fifo_mode()
387 	val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_fifo_mode()
390 		writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_fifo_mode()
393 static void geni_se_select_dma_mode(struct geni_se *se)  in geni_se_select_dma_mode()  argument
395 	u32 proto = geni_se_read_proto(se);  in geni_se_select_dma_mode()
398 	geni_se_irq_clear(se);  in geni_se_select_dma_mode()
403 		val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_dma_mode()
407 			writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_dma_mode()
410 	val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_dma_mode()
413 		writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_dma_mode()
416 static void geni_se_select_gpi_mode(struct geni_se *se)  in geni_se_select_gpi_mode()  argument
420 	geni_se_irq_clear(se);  in geni_se_select_gpi_mode()
422 	writel(0, se->base + SE_IRQ_EN);  in geni_se_select_gpi_mode()
424 	val = readl(se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_gpi_mode()
427 	writel(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_gpi_mode()
429 	writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_gpi_mode()
431 	val = readl(se->base + SE_GSI_EVENT_EN);  in geni_se_select_gpi_mode()
433 	writel(val, se->base + SE_GSI_EVENT_EN);  in geni_se_select_gpi_mode()
441 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)  in geni_se_select_mode()  argument
447 		geni_se_select_fifo_mode(se);  in geni_se_select_mode()
450 		geni_se_select_dma_mode(se);  in geni_se_select_mode()
453 		geni_se_select_gpi_mode(se);  in geni_se_select_mode()
524 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,  in geni_se_config_packing()  argument
559 		writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);  in geni_se_config_packing()
560 		writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);  in geni_se_config_packing()
563 		writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);  in geni_se_config_packing()
564 		writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);  in geni_se_config_packing()
575 		writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);  in geni_se_config_packing()
579 static void geni_se_clks_off(struct geni_se *se)  in geni_se_clks_off()  argument
581 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_clks_off()
583 	clk_disable_unprepare(se->clk);  in geni_se_clks_off()
594 int geni_se_resources_off(struct geni_se *se)  in geni_se_resources_off()  argument
598 	if (has_acpi_companion(se->dev))  in geni_se_resources_off()
601 	ret = pinctrl_pm_select_sleep_state(se->dev);  in geni_se_resources_off()
605 	geni_se_clks_off(se);  in geni_se_resources_off()
610 static int geni_se_clks_on(struct geni_se *se)  in geni_se_clks_on()  argument
613 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_clks_on()
619 	ret = clk_prepare_enable(se->clk);  in geni_se_clks_on()
632 int geni_se_resources_on(struct geni_se *se)  in geni_se_resources_on()  argument
636 	if (has_acpi_companion(se->dev))  in geni_se_resources_on()
639 	ret = geni_se_clks_on(se);  in geni_se_resources_on()
643 	ret = pinctrl_pm_select_default_state(se->dev);  in geni_se_resources_on()
645 		geni_se_clks_off(se);  in geni_se_resources_on()
664 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)  in geni_se_clk_tbl_get()  argument
669 	if (se->clk_perf_tbl) {  in geni_se_clk_tbl_get()
670 		*tbl = se->clk_perf_tbl;  in geni_se_clk_tbl_get()
671 		return se->num_clk_levels;  in geni_se_clk_tbl_get()
674 	se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,  in geni_se_clk_tbl_get()
675 					sizeof(*se->clk_perf_tbl),  in geni_se_clk_tbl_get()
677 	if (!se->clk_perf_tbl)  in geni_se_clk_tbl_get()
681 		freq = clk_round_rate(se->clk, freq + 1);  in geni_se_clk_tbl_get()
683 		    (i > 0 && freq == se->clk_perf_tbl[i - 1]))  in geni_se_clk_tbl_get()
685 		se->clk_perf_tbl[i] = freq;  in geni_se_clk_tbl_get()
687 	se->num_clk_levels = i;  in geni_se_clk_tbl_get()
688 	*tbl = se->clk_perf_tbl;  in geni_se_clk_tbl_get()
689 	return se->num_clk_levels;  in geni_se_clk_tbl_get()
712 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,  in geni_se_clk_freq_match()  argument
723 	num_clk_levels = geni_se_clk_tbl_get(se, &tbl);  in geni_se_clk_freq_match()
771 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)  in geni_se_tx_init_dma()  argument
778 	writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);  in geni_se_tx_init_dma()
779 	writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);  in geni_se_tx_init_dma()
780 	writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);  in geni_se_tx_init_dma()
781 	writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);  in geni_se_tx_init_dma()
782 	writel(len, se->base + SE_DMA_TX_LEN);  in geni_se_tx_init_dma()
797 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,  in geni_se_tx_dma_prep()  argument
800 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_tx_dma_prep()
809 	geni_se_tx_init_dma(se, *iova, len);  in geni_se_tx_dma_prep()
822 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)  in geni_se_rx_init_dma()  argument
829 	writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);  in geni_se_rx_init_dma()
830 	writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);  in geni_se_rx_init_dma()
831 	writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);  in geni_se_rx_init_dma()
833 	writel_relaxed(0, se->base + SE_DMA_RX_ATTR);  in geni_se_rx_init_dma()
834 	writel(len, se->base + SE_DMA_RX_LEN);  in geni_se_rx_init_dma()
849 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,  in geni_se_rx_dma_prep()  argument
852 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_rx_dma_prep()
861 	geni_se_rx_init_dma(se, *iova, len);  in geni_se_rx_dma_prep()
874 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)  in geni_se_tx_dma_unprep()  argument
876 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_tx_dma_unprep()
891 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)  in geni_se_rx_dma_unprep()  argument
893 	struct geni_wrapper *wrapper = se->wrapper;  in geni_se_rx_dma_unprep()
900 int geni_icc_get(struct geni_se *se, const char *icc_ddr)  in geni_icc_get()  argument
905 	if (has_acpi_companion(se->dev))  in geni_icc_get()
908 	for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {  in geni_icc_get()
912 		se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);  in geni_icc_get()
913 		if (IS_ERR(se->icc_paths[i].path))  in geni_icc_get()
920 	err = PTR_ERR(se->icc_paths[i].path);  in geni_icc_get()
922 		dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",  in geni_icc_get()
929 int geni_icc_set_bw(struct geni_se *se)  in geni_icc_set_bw()  argument
933 	for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {  in geni_icc_set_bw()
934 		ret = icc_set_bw(se->icc_paths[i].path,  in geni_icc_set_bw()
935 			se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);  in geni_icc_set_bw()
937 			dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",  in geni_icc_set_bw()
947 void geni_icc_set_tag(struct geni_se *se, u32 tag)  in geni_icc_set_tag()  argument
951 	for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)  in geni_icc_set_tag()
952 		icc_set_tag(se->icc_paths[i].path, tag);  in geni_icc_set_tag()
957 int geni_icc_enable(struct geni_se *se)  in geni_icc_enable()  argument
961 	for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {  in geni_icc_enable()
962 		ret = icc_enable(se->icc_paths[i].path);  in geni_icc_enable()
964 			dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",  in geni_icc_enable()
974 int geni_icc_disable(struct geni_se *se)  in geni_icc_disable()  argument
978 	for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {  in geni_icc_disable()
979 		ret = icc_disable(se->icc_paths[i].path);  in geni_icc_disable()
981 			dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",  in geni_icc_disable()
1099 static int geni_configure_xfer_mode(struct geni_se *se, enum geni_se_xfer_mode mode)  in geni_configure_xfer_mode()  argument
1104 		geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);  in geni_configure_xfer_mode()
1105 		writel(0x0, se->base + SE_IRQ_EN);  in geni_configure_xfer_mode()
1107 		       se->base + SE_GSI_EVENT_EN);  in geni_configure_xfer_mode()
1111 		geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);  in geni_configure_xfer_mode()
1113 		       se->base + SE_IRQ_EN);  in geni_configure_xfer_mode()
1114 		writel(0x0, se->base + SE_GSI_EVENT_EN);  in geni_configure_xfer_mode()
1118 		geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);  in geni_configure_xfer_mode()
1120 		       se->base + SE_IRQ_EN);  in geni_configure_xfer_mode()
1121 		writel(0x0, se->base + SE_GSI_EVENT_EN);  in geni_configure_xfer_mode()
1125 		dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", mode);  in geni_configure_xfer_mode()
1137 static void geni_enable_interrupts(struct geni_se *se)  in geni_enable_interrupts()  argument
1142 	writel(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN);  in geni_enable_interrupts()
1147 	writel(val, se->base + SE_GENI_S_IRQ_ENABLE);  in geni_enable_interrupts()
1151 	writel(val, se->base + SE_DMA_TX_IRQ_EN_SET);  in geni_enable_interrupts()
1154 	writel(val, se->base + SE_DMA_RX_IRQ_EN_SET);  in geni_enable_interrupts()
1165 static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol, u16 fw_version)  in geni_write_fw_revision()  argument
1172 	writel(reg, se->base + SE_GENI_FW_REVISION);  in geni_write_fw_revision()
1173 	writel(reg, se->base + SE_GENI_S_FW_REVISION);  in geni_write_fw_revision()
1187 static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw,  in geni_load_se_fw()  argument
1196 	hdr = geni_find_protocol_fw(se->dev, fw, protocol);  in geni_load_se_fw()
1204 	ret = geni_icc_set_bw(se);  in geni_load_se_fw()
1208 	ret = geni_icc_enable(se);  in geni_load_se_fw()
1212 	ret = geni_se_resources_on(se);  in geni_load_se_fw()
1220 	geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_DISABLE);  in geni_load_se_fw()
1223 	geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON);  in geni_load_se_fw()
1226 	geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_CLK_CGC_ON);  in geni_load_se_fw()
1232 	writel(0x0, se->base + GENI_OUTPUT_CTRL);  in geni_load_se_fw()
1235 	geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);  in geni_load_se_fw()
1236 	writel(0x0, se->base + SE_GENI_CLK_CTRL);  in geni_load_se_fw()
1237 	geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);  in geni_load_se_fw()
1242 	geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value);  in geni_load_se_fw()
1245 	writel(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL);  in geni_load_se_fw()
1248 	writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_INIT_CFG_REVISION);  in geni_load_se_fw()
1249 	writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_S_INIT_CFG_REVISION);  in geni_load_se_fw()
1254 		       se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32)));  in geni_load_se_fw()
1257 	reg_value = geni_se_get_rx_fifo_depth(se);  in geni_load_se_fw()
1258 	writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG);  in geni_load_se_fw()
1261 	geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK);  in geni_load_se_fw()
1263 	ret = geni_configure_xfer_mode(se, mode);  in geni_load_se_fw()
1267 	geni_enable_interrupts(se);  in geni_load_se_fw()
1269 	geni_write_fw_revision(se, le16_to_cpu(hdr->serial_protocol), le16_to_cpu(hdr->fw_version));  in geni_load_se_fw()
1272 	memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data,  in geni_load_se_fw()
1276 	writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG);  in geni_load_se_fw()
1279 	geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);  in geni_load_se_fw()
1280 	geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL);  in geni_load_se_fw()
1281 	geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);  in geni_load_se_fw()
1284 	geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN);  in geni_load_se_fw()
1288 		geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);  in geni_load_se_fw()
1290 		geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);  in geni_load_se_fw()
1293 	geni_se_resources_off(se);  in geni_load_se_fw()
1296 	geni_icc_disable(se);  in geni_load_se_fw()
1312 int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol)  in geni_load_se_firmware()  argument
1320 		dev_err(se->dev, "Invalid geni-se protocol: %d", protocol);  in geni_load_se_firmware()
1324 	ret = device_property_read_string(se->wrapper->dev, "firmware-name", &fw_name);  in geni_load_se_firmware()
1326 		dev_err(se->dev, "Failed to read firmware-name property: %d\n", ret);  in geni_load_se_firmware()
1330 	if (of_property_read_bool(se->dev->of_node, "qcom,enable-gsi-dma"))  in geni_load_se_firmware()
1337 	ret = request_firmware(&fw, fw_name, se->dev);  in geni_load_se_firmware()
1342 		dev_err(se->dev, "Failed to request firmware '%s' for protocol %d: ret: %d\n",  in geni_load_se_firmware()
1347 	ret = geni_load_se_fw(se, fw, mode, protocol);  in geni_load_se_firmware()
1351 		dev_err(se->dev, "Failed to load SE firmware for protocol %d: ret: %d\n",  in geni_load_se_firmware()
1356 	dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mode: %d\n",  in geni_load_se_firmware()