Lines Matching +full:v +full:- +full:pos +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/nvmem-consumer.h>
147 inode->i_private); \
162 inode->i_private); \
177 * enum svsb_sw_id - SVS Bank Software ID
193 * enum svsb_type - SVS Bank 2-line: Type and Role
194 * @SVSB_TYPE_NONE: One-line type Bank - Global role
195 * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role
196 * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
207 * enum svsb_phase - svs bank phase enumeration
218 * svs bank general phase-enabled order:
219 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
373 * struct svs_platform - svs platform control
414 * struct svs_bank_pdata - SVS Bank immutable config parameters
419 * @ctl0: TS-x selection
422 * @turn_freq_base: Reference frequency for 2-line turn point
435 * @type: SVS Bank Type (1 or 2-line) and Role (high/low)
468 * struct svs_bank - svs bank representation
502 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
559 return readl_relaxed(svsp->base + svsp->regs[rg_i]);
565 writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
570 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
582 return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
587 const struct svs_bank_pdata *bdata = &svsb->pdata;
591 for (i = 0; i < bdata->opp_count; i++) {
592 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
593 svsb->opp_dfreq[i],
596 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
597 svsb->opp_dfreq[i], PTR_ERR(opp));
602 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
603 bdata->volt_step,
604 bdata->volt_base);
613 int ret = -EPERM, tzone_temp = 0;
614 const struct svs_bank_pdata *bdata = &svsb->pdata;
617 mutex_lock(&svsb->lock);
620 * 2-line bank updates its corresponding opp volts.
621 * 1-line bank updates all opp volts.
623 if (bdata->type == SVSB_TYPE_HIGH) {
625 opp_stop = svsb->turn_pt;
626 } else if (bdata->type == SVSB_TYPE_LOW) {
627 opp_start = svsb->turn_pt;
628 opp_stop = bdata->opp_count;
631 opp_stop = bdata->opp_count;
635 if (!IS_ERR_OR_NULL(svsb->tzd)) {
636 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
637 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
638 svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
639 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
640 bdata->tzone_name, ret, svsb->temp);
641 svsb->phase = SVSB_PHASE_ERROR;
644 if (tzone_temp >= bdata->tzone_htemp)
645 temp_voffset += bdata->tzone_htemp_voffset;
646 else if (tzone_temp <= bdata->tzone_ltemp)
647 temp_voffset += bdata->tzone_ltemp_voffset;
649 /* 2-line bank update all opp volts when running mon mode */
650 if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH ||
651 bdata->type == SVSB_TYPE_LOW)) {
653 opp_stop = bdata->opp_count;
659 switch (svsb->phase) {
661 opp_volt = svsb->opp_dvolt[i];
668 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
670 bdata->volt_step,
671 bdata->volt_base);
674 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
675 ret = -EINVAL;
679 opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
680 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
681 svsb->opp_dfreq[i],
683 svsb->opp_dvolt[i]);
685 dev_err(svsb->dev, "set %uuV fail: %d\n",
692 mutex_unlock(&svsb->lock);
702 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
711 svsb->phase = SVSB_PHASE_ERROR;
718 struct svs_platform *svsp = (struct svs_platform *)m->private;
723 for (i = 0; i < svsp->efuse_max; i++)
724 if (svsp->efuse && svsp->efuse[i])
726 i, svsp->efuse[i]);
728 for (i = 0; i < svsp->tefuse_max; i++)
729 if (svsp->tefuse)
731 i, svsp->tefuse[i]);
733 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
734 svsb = &svsp->banks[idx];
747 svs_reg_addr = (unsigned long)(svsp->base +
748 svsp->regs[j]);
750 svs_reg_addr, svsb->reg_data[i][j]);
760 static int svs_enable_debug_show(struct seq_file *m, void *v)
762 struct svs_bank *svsb = (struct svs_bank *)m->private;
764 switch (svsb->phase) {
787 size_t count, loff_t *pos)
789 struct svs_bank *svsb = file_inode(filp)->i_private;
790 struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
795 return -EINVAL;
807 svsb->mode_support = SVSB_MODE_ALL_DISABLE;
817 static int svs_status_debug_show(struct seq_file *m, void *v)
819 struct svs_bank *svsb = (struct svs_bank *)m->private;
824 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
827 svsb->name, svsb->vbin_turn_pt, svsb->turn_pt);
830 svsb->name, tzone_temp, svsb->vbin_turn_pt,
831 svsb->turn_pt);
833 for (i = 0; i < svsb->pdata.opp_count; i++) {
834 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
835 svsb->opp_dfreq[i], true);
838 svsb->name, svsb->opp_dfreq[i],
844 i, svsb->opp_dfreq[i], i,
847 i, svsb->volt[i], i, svsb->freq_pct[i]);
879 dev_err(svsp->dev, "cannot create %s: %ld\n",
889 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
895 for (idx = 0; idx < svsp->bank_max; idx++) {
896 svsb = &svsp->banks[idx];
898 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
901 svsb_dir = debugfs_create_dir(svsb->name, svs_dir);
903 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
904 d, svsb->name, PTR_ERR(svsb_dir));
913 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
914 d, svsb->name, svsb_entries[i].name,
933 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));
940 const struct svs_bank_pdata *bdata = &svsb->pdata;
941 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
943 u32 middle_index = (bdata->opp_count / 2);
945 if (svsb->phase == SVSB_PHASE_MON &&
946 svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
952 /* Target is to set svsb->volt[] by algorithm */
954 if (bdata->type == SVSB_TYPE_HIGH) {
955 /* volt[0] ~ volt[turn_pt - 1] */
960 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
963 } else if (bdata->type == SVSB_TYPE_LOW) {
964 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
965 j = bdata->opp_count - 7;
966 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
968 for (i = j; i < bdata->opp_count; i++) {
972 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
976 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
978 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
979 svsb->freq_pct[j],
980 svsb->volt[turn_pt],
981 svsb->volt[j],
982 svsb->freq_pct[i]);
985 if (bdata->type == SVSB_TYPE_HIGH) {
986 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */
987 j = turn_pt - 7;
988 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
994 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
998 /* volt[1] ~ volt[j - 1] by interpolate */
1000 svsb->volt[i] = interpolate(svsb->freq_pct[0],
1001 svsb->freq_pct[j],
1002 svsb->volt[0],
1003 svsb->volt[j],
1004 svsb->freq_pct[i]);
1005 } else if (bdata->type == SVSB_TYPE_LOW) {
1006 /* volt[turn_pt] ~ volt[opp_count - 1] */
1007 for (i = turn_pt; i < bdata->opp_count; i++) {
1011 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
1017 if (bdata->type == SVSB_TYPE_HIGH) {
1019 opp_stop = svsb->turn_pt;
1020 } else if (bdata->type == SVSB_TYPE_LOW) {
1021 opp_start = svsb->turn_pt;
1022 opp_stop = bdata->opp_count;
1026 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
1027 svsb->volt[i] -= svsb->dvt_fixed;
1030 if (svsb->opp_dfreq[0] > svsb->freq_base) {
1031 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1032 bdata->volt_step,
1033 bdata->volt_base);
1036 for (i = 0; i < bdata->opp_count; i++) {
1037 if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1038 svsb->vbin_turn_pt = i;
1044 for (i = 1; i < svsb->vbin_turn_pt; i++)
1045 svsb->volt[i] = interpolate(svsb->freq_pct[0],
1046 svsb->freq_pct[svsb->vbin_turn_pt],
1047 svsb->volt[0],
1048 svsb->volt[svsb->vbin_turn_pt],
1049 svsb->freq_pct[i]);
1055 const struct svs_bank_pdata *bdata = &svsb->pdata;
1058 u32 middle_index = (bdata->opp_count / 2);
1060 for (i = 0; i < bdata->opp_count; i++) {
1061 if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) {
1062 svsb->turn_pt = i;
1067 turn_pt = svsb->turn_pt;
1071 if (bdata->type == SVSB_TYPE_HIGH) {
1078 freq_pct30 = svsb->freq_pct[0];
1080 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */
1085 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1088 } else if (bdata->type == SVSB_TYPE_LOW) {
1091 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
1093 freq_pct30 = svsb->freq_pct[turn_pt];
1095 j = bdata->opp_count - 7;
1096 for (i = j; i < bdata->opp_count; i++) {
1100 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1105 if (bdata->type == SVSB_TYPE_HIGH) {
1108 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
1110 freq_pct30 = svsb->freq_pct[0];
1112 j = turn_pt - 7;
1117 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1120 } else if (bdata->type == SVSB_TYPE_LOW) {
1121 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
1122 for (i = turn_pt; i < bdata->opp_count; i++) {
1126 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1138 const struct svs_bank_pdata *bdata = &svsb->pdata;
1142 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1143 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1144 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1145 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1148 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1149 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1150 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1151 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1154 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
1155 svsb->freq_pct[i + 2],
1156 svsb->volt[i],
1157 svsb->volt[i + 2],
1158 svsb->freq_pct[i + 1]);
1160 svsb->volt[15] = interpolate(svsb->freq_pct[12],
1161 svsb->freq_pct[14],
1162 svsb->volt[12],
1163 svsb->volt[14],
1164 svsb->freq_pct[15]);
1166 for (i = 0; i < bdata->opp_count; i++)
1167 svsb->volt[i] += svsb->volt_od;
1170 if (svsb->opp_dfreq[0] > svsb->freq_base) {
1171 svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1172 bdata->volt_step,
1173 bdata->volt_base);
1176 for (i = 0; i < bdata->opp_count; i++) {
1177 if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1178 svsb->vbin_turn_pt = i;
1184 for (i = 1; i < svsb->vbin_turn_pt; i++)
1185 svsb->volt[i] = interpolate(svsb->freq_pct[0],
1186 svsb->freq_pct[svsb->vbin_turn_pt],
1187 svsb->volt[0],
1188 svsb->volt[svsb->vbin_turn_pt],
1189 svsb->freq_pct[i]);
1197 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1198 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1199 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1200 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1202 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1203 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1204 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1205 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1215 struct svs_bank *svsb = &svsp->banks[bank_idx];
1216 const struct svs_bank_pdata *bdata = &svsb->pdata;
1221 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1222 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1225 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) |
1226 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1227 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1230 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1231 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1234 svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG);
1235 svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG);
1238 bdata->set_freq_pct(svsp, svsb);
1242 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1243 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1248 svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT);
1249 svs_writel_relaxed(svsp, bdata->ctl0, CTL0);
1254 svs_writel_relaxed(svsp, bdata->vboot, VBOOT);
1259 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1260 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1266 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1267 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1273 dev_err(svsb->dev, "requested unknown target phase: %u\n",
1283 struct svs_bank *svsb = &svsp->banks[bank_idx];
1287 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1293 struct svs_bank *svsb = &svsp->banks[bank_idx];
1295 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1297 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1300 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1303 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1307 svsb->phase = SVSB_PHASE_ERROR;
1315 struct svs_bank *svsb = &svsp->banks[bank_idx];
1318 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1325 svsb->phase = SVSB_PHASE_INIT01;
1327 svsb->dc_voffset_in = val & GENMASK(15, 0);
1328 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1329 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1330 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1331 svsb->dc_voffset_in = 0;
1333 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1338 svsb->core_sel &= ~SVSB_DET_CLK_EN;
1344 struct svs_bank *svsb = &svsp->banks[bank_idx];
1345 const struct svs_bank_pdata *bdata = &svsb->pdata;
1347 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1354 svsb->phase = SVSB_PHASE_INIT02;
1355 bdata->get_volts(svsp, svsb);
1364 struct svs_bank *svsb = &svsp->banks[bank_idx];
1365 const struct svs_bank_pdata *bdata = &svsb->pdata;
1369 svsb->phase = SVSB_PHASE_MON;
1370 bdata->get_volts(svsp, svsb);
1372 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1384 for (idx = 0; idx < svsp->bank_max; idx++) {
1385 svsb = &svsp->banks[idx];
1386 bdata = &svsb->pdata;
1387 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1392 if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) {
1418 if (svsb->phase == SVSB_PHASE_INIT01 ||
1419 svsb->phase == SVSB_PHASE_INIT02)
1420 complete(&svsb->init_completion);
1429 for (i = 0; i < svsp->bank_max; i++)
1430 if (svsp->banks[i].mode_support & mode)
1450 /* Svs bank init01 preparation - power enable */
1451 for (idx = 0; idx < svsp->bank_max; idx++) {
1452 svsb = &svsp->banks[idx];
1453 bdata = &svsb->pdata;
1455 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1458 ret = regulator_enable(svsb->buck);
1460 dev_err(svsb->dev, "%s enable fail: %d\n",
1461 bdata->buck_name, ret);
1466 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST);
1468 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1470 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1471 if (!pm_runtime_enabled(svsb->opp_dev)) {
1472 pm_runtime_enable(svsb->opp_dev);
1473 svsb->pm_runtime_enabled_count++;
1476 ret = pm_runtime_resume_and_get(svsb->opp_dev);
1478 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1485 * Svs bank init01 preparation - vboot voltage adjustment
1489 for (idx = 0; idx < svsp->bank_max; idx++) {
1490 svsb = &svsp->banks[idx];
1491 bdata = &svsb->pdata;
1493 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1501 opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1502 bdata->volt_step,
1503 bdata->volt_base);
1505 for (i = 0; i < bdata->opp_count; i++) {
1506 opp_freq = svsb->opp_dfreq[i];
1507 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1508 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
1514 dev_err(svsb->dev,
1522 ret = dev_pm_opp_disable(svsb->opp_dev,
1523 svsb->opp_dfreq[i]);
1525 dev_err(svsb->dev,
1527 svsb->opp_dfreq[i], ret);
1535 for (idx = 0; idx < svsp->bank_max; idx++) {
1536 svsb = &svsp->banks[idx];
1537 bdata = &svsb->pdata;
1539 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1542 opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1543 bdata->volt_step,
1544 bdata->volt_base);
1546 buck_volt = regulator_get_voltage(svsb->buck);
1548 dev_err(svsb->dev,
1551 ret = -EPERM;
1559 time_left = wait_for_completion_timeout(&svsb->init_completion,
1562 dev_err(svsb->dev, "init01 completion timeout\n");
1563 ret = -EBUSY;
1569 for (idx = 0; idx < svsp->bank_max; idx++) {
1570 svsb = &svsp->banks[idx];
1571 bdata = &svsb->pdata;
1573 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1576 for (i = 0; i < bdata->opp_count; i++) {
1577 r = dev_pm_opp_enable(svsb->opp_dev,
1578 svsb->opp_dfreq[i]);
1580 dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1581 svsb->opp_dfreq[i], r);
1584 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1585 r = pm_runtime_put_sync(svsb->opp_dev);
1587 dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1589 if (svsb->pm_runtime_enabled_count > 0) {
1590 pm_runtime_disable(svsb->opp_dev);
1591 svsb->pm_runtime_enabled_count--;
1595 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL);
1597 dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1599 r = regulator_disable(svsb->buck);
1601 dev_err(svsb->dev, "%s disable fail: %d\n",
1602 bdata->buck_name, r);
1622 for (idx = 0; idx < svsp->bank_max; idx++) {
1623 svsb = &svsp->banks[idx];
1625 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1628 reinit_completion(&svsb->init_completion);
1633 time_left = wait_for_completion_timeout(&svsb->init_completion,
1636 dev_err(svsb->dev, "init02 completion timeout\n");
1637 ret = -EBUSY;
1643 * 2-line high/low bank update its corresponding opp voltages only.
1647 for (idx = 0; idx < svsp->bank_max; idx++) {
1648 svsb = &svsp->banks[idx];
1649 bdata = &svsb->pdata;
1651 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1654 if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) {
1656 dev_err(svsb->dev, "sync volt fail\n");
1657 ret = -EPERM;
1666 for (idx = 0; idx < svsp->bank_max; idx++) {
1667 svsb = &svsp->banks[idx];
1680 for (idx = 0; idx < svsp->bank_max; idx++) {
1681 svsb = &svsp->banks[idx];
1683 if (!(svsb->mode_support & SVSB_MODE_MON))
1715 for (idx = 0; idx < svsp->bank_max; idx++) {
1716 struct svs_bank *svsb = &svsp->banks[idx];
1721 ret = reset_control_assert(svsp->rst);
1723 dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1727 clk_disable_unprepare(svsp->main_clk);
1737 ret = clk_prepare_enable(svsp->main_clk);
1739 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1743 ret = reset_control_deassert(svsp->rst);
1745 dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1758 dev_err(svsp->dev, "assert reset: %d\n",
1759 reset_control_assert(svsp->rst));
1762 clk_disable_unprepare(svsp->main_clk);
1776 dev_set_drvdata(svsp->dev, svsp);
1778 for (idx = 0; idx < svsp->bank_max; idx++) {
1779 svsb = &svsp->banks[idx];
1780 bdata = &svsb->pdata;
1782 if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) {
1783 dev_err(svsb->dev, "unknown bank sw_id or type\n");
1784 return -EINVAL;
1787 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL);
1788 if (!svsb->dev)
1789 return -ENOMEM;
1791 svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s",
1792 svs_swid_names[bdata->sw_id],
1793 svs_type_names[bdata->type]);
1794 if (!svsb->name)
1795 return -ENOMEM;
1797 ret = dev_set_name(svsb->dev, "%s", svsb->name);
1801 dev_set_drvdata(svsb->dev, svsp);
1803 ret = devm_pm_opp_of_add_table(svsb->opp_dev);
1805 dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1809 mutex_init(&svsb->lock);
1810 init_completion(&svsb->init_completion);
1812 if (svsb->mode_support & SVSB_MODE_INIT01) {
1813 svsb->buck = devm_regulator_get_optional(svsb->opp_dev,
1814 bdata->buck_name);
1815 if (IS_ERR(svsb->buck)) {
1816 dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1817 bdata->buck_name);
1818 return PTR_ERR(svsb->buck);
1822 if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
1824 "%s-thermal", bdata->tzone_name);
1825 svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
1826 if (IS_ERR(svsb->tzd)) {
1827 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1829 return PTR_ERR(svsb->tzd);
1833 count = dev_pm_opp_get_opp_count(svsb->opp_dev);
1834 if (bdata->opp_count != count) {
1835 dev_err(svsb->dev,
1837 bdata->opp_count, count);
1841 for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) {
1842 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq);
1844 dev_err(svsb->dev, "cannot find freq = %ld\n",
1849 svsb->opp_dfreq[i] = freq;
1850 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1851 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i],
1852 svsb->freq_base);
1866 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name);
1868 dev_err(svsp->dev, "no \"%s\"? %ld\n",
1889 if (fmap->index < 0)
1892 val = fuse_array[fmap->index] >> fmap->ofst;
1893 val &= GENMASK(nbits - 1, 0);
1903 for (i = 0; i < svsp->efuse_max; i++) {
1904 if (svsp->efuse[i])
1917 const struct svs_fusemap *gfmap = pdata->glb_fuse_map;
1926 /* Get golden temperature from SVS-Thermal calibration */
1927 val = svs_get_fuse_val(svsp->tefuse, &tfm, 8);
1933 ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8);
1934 vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2);
1936 for (i = 0; i < svsp->bank_max; i++) {
1937 struct svs_bank *svsb = &svsp->banks[i];
1938 const struct svs_bank_pdata *bdata = &svsb->pdata;
1939 const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1942 svsb->vmin = 0x1e;
1945 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1947 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1948 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1949 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1950 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1951 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1952 svsb->vmax += svsb->dvt_fixed;
1954 svsb->mts = (svsp->ts_coeff * 2) / 1000;
1955 svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4;
1971 for (i = 0; i < svsp->efuse_max; i++)
1972 if (svsp->efuse[i])
1973 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1974 i, svsp->efuse[i]);
1976 if (!svsp->efuse[2]) {
1977 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1982 ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4);
1984 for (idx = 0; idx < svsp->bank_max; idx++) {
1985 svsb = &svsp->banks[idx];
1986 bdata = &svsb->pdata;
1987 const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1990 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1992 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1993 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1994 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1995 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1996 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1998 switch (bdata->sw_id) {
2002 svsb->volt_od += 10;
2004 svsb->volt_od += 2;
2008 svsb->volt_od += 15;
2010 svsb->volt_od += 12;
2014 svsb->freq_base = 800000000; /* 800MHz */
2015 svsb->dvt_fixed = 2;
2019 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2025 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
2026 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
2028 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
2029 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
2030 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
2031 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
2032 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
2033 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
2035 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
2036 adc_cali_en_t = svsp->tefuse[0] & BIT(0);
2037 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
2039 ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
2043 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
2047 o_slope = 1534 - o_slope * 10;
2053 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
2054 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
2055 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
2056 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
2057 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
2058 o_vtsabb < -8 || o_vtsabb > 484 ||
2060 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
2064 ge = ((adc_ge_t - 512) * 10000) / 4096;
2065 oe = (adc_oe_t - 512);
2068 format[0] = (o_vtsmcu[0] + 3350 - oe);
2069 format[1] = (o_vtsmcu[1] + 3350 - oe);
2070 format[2] = (o_vtsmcu[2] + 3350 - oe);
2071 format[3] = (o_vtsmcu[3] + 3350 - oe);
2072 format[4] = (o_vtsmcu[4] + 3350 - oe);
2073 format[5] = (o_vtsabb + 3350 - oe);
2081 for (idx = 0; idx < svsp->bank_max; idx++) {
2082 svsb = &svsp->banks[idx];
2083 bdata = &svsb->pdata;
2084 svsb->mts = mts;
2086 switch (bdata->sw_id) {
2100 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2109 svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
2115 for (idx = 0; idx < svsp->bank_max; idx++) {
2116 svsb = &svsp->banks[idx];
2117 svsb->mode_support &= ~SVSB_MODE_MON;
2131 dev_err(svsp->dev, "cannot find %s node\n", node_name);
2132 return ERR_PTR(-ENODEV);
2138 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2139 return ERR_PTR(-ENXIO);
2142 return &pdev->dev;
2155 sup_link = device_link_add(svsp->dev, dev,
2158 dev_err(svsp->dev, "sup_link is NULL\n");
2159 return ERR_PTR(-EINVAL);
2162 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
2163 return ERR_PTR(-EPROBE_DEFER);
2173 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2174 if (IS_ERR(svsp->rst))
2175 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2178 dev = svs_add_device_link(svsp, "thermal-sensor");
2180 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2183 for (idx = 0; idx < svsp->bank_max; idx++) {
2184 struct svs_bank *svsb = &svsp->banks[idx];
2185 const struct svs_bank_pdata *bdata = &svsb->pdata;
2187 switch (bdata->sw_id) {
2190 svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2193 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2196 if (bdata->type == SVSB_TYPE_LOW)
2197 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2199 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2202 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2203 return -EINVAL;
2206 if (IS_ERR(svsb->opp_dev))
2207 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2220 dev = svs_add_device_link(svsp, "thermal-sensor");
2222 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2225 for (idx = 0; idx < svsp->bank_max; idx++) {
2226 struct svs_bank *svsb = &svsp->banks[idx];
2227 const struct svs_bank_pdata *bdata = &svsb->pdata;
2229 switch (bdata->sw_id) {
2232 svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2235 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2238 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2241 dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2242 return -EINVAL;
2245 if (IS_ERR(svsb->opp_dev))
2246 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2489 .tzone_name = "cpu-big",
2523 .tzone_name = "cpu-little",
2740 .name = "mt8195-svs",
2753 .name = "mt8192-svs",
2762 { -1, 0 }, { 19, 4 }
2767 .name = "mt8188-svs",
2776 { -1, 0 }, { -1, 0 }
2781 .name = "mt8186-svs",
2790 { -1, 0 }, { -1, 0 }
2795 .name = "mt8183-svs",
2803 { 0, 4 }, { -1, 0 }
2808 { .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data },
2809 { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data },
2810 { .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data },
2811 { .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data },
2812 { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data },
2823 svsp_data = of_device_get_match_data(&pdev->dev);
2825 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2827 return -ENOMEM;
2829 svsp->dev = &pdev->dev;
2830 svsp->banks = svsp_data->banks;
2831 svsp->regs = svsp_data->regs;
2832 svsp->bank_max = svsp_data->bank_max;
2833 svsp->ts_coeff = svsp_data->ts_coeff;
2835 ret = svsp_data->probe(svsp);
2839 ret = svs_get_efuse_data(svsp, "svs-calibration-data",
2840 &svsp->efuse, &svsp->efuse_max);
2842 return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n");
2844 ret = svs_get_efuse_data(svsp, "t-calibration-data",
2845 &svsp->tefuse, &svsp->tefuse_max);
2847 dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n");
2851 if (!svsp_data->efuse_parsing(svsp, svsp_data)) {
2852 ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n");
2858 dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n");
2868 svsp->main_clk = devm_clk_get(svsp->dev, "main");
2869 if (IS_ERR(svsp->main_clk)) {
2870 ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk),
2875 ret = clk_prepare_enable(svsp->main_clk);
2877 dev_err_probe(svsp->dev, ret, "cannot enable main clk\n");
2881 svsp->base = of_iomap(svsp->dev->of_node, 0);
2882 if (IS_ERR_OR_NULL(svsp->base)) {
2883 ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n");
2887 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2888 IRQF_ONESHOT, svsp_data->name, svsp);
2890 dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq);
2896 dev_err_probe(svsp->dev, ret, "svs start fail\n");
2903 dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n");
2911 iounmap(svsp->base);
2913 clk_disable_unprepare(svsp->main_clk);
2915 kfree(svsp->tefuse);
2917 kfree(svsp->efuse);
2926 .name = "mtk-svs",