Lines Matching defs:svsp
405 bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata);
406 int (*probe)(struct svs_platform *svsp);
463 void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb);
464 void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb);
557 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
559 return readl_relaxed(svsp->base + svsp->regs[rg_i]);
562 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
565 writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
568 static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb)
570 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
697 static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp,
706 svs_switch_bank(svsp, svsb);
707 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
708 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
718 struct svs_platform *svsp = (struct svs_platform *)m->private;
723 for (i = 0; i < svsp->efuse_max; i++)
724 if (svsp->efuse && svsp->efuse[i])
726 i, svsp->efuse[i]);
728 for (i = 0; i < svsp->tefuse_max; i++)
729 if (svsp->tefuse)
731 i, svsp->tefuse[i]);
733 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
734 svsb = &svsp->banks[idx];
747 svs_reg_addr = (unsigned long)(svsp->base +
748 svsp->regs[j]);
790 struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
806 svs_bank_disable_and_restore_default_volts(svsp, svsb);
856 static int svs_create_debug_cmds(struct svs_platform *svsp)
879 dev_err(svsp->dev, "cannot create %s: %ld\n",
886 svs_dir, svsp,
889 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
895 for (idx = 0; idx < svsp->bank_max; idx++) {
896 svsb = &svsp->banks[idx];
903 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
913 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
938 static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb)
949 vop74 = svs_readl_relaxed(svsp, VOP74);
950 vop30 = svs_readl_relaxed(svsp, VOP30);
1053 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb)
1132 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
1133 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
1136 static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1141 temp = svs_readl_relaxed(svsp, VOP74);
1147 temp = svs_readl_relaxed(svsp, VOP30);
1193 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1207 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
1208 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
1211 static void svs_set_bank_phase(struct svs_platform *svsp,
1215 struct svs_bank *svsb = &svsp->banks[bank_idx];
1219 svs_switch_bank(svsp, svsb);
1223 svs_writel_relaxed(svsp, des_char, DESCHAR);
1228 svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
1232 svs_writel_relaxed(svsp, det_char, DETCHAR);
1234 svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG);
1235 svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG);
1236 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);
1238 bdata->set_freq_pct(svsp, svsb);
1244 svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
1246 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
1247 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
1248 svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT);
1249 svs_writel_relaxed(svsp, bdata->ctl0, CTL0);
1250 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1254 svs_writel_relaxed(svsp, bdata->vboot, VBOOT);
1255 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1256 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
1261 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1262 svs_writel_relaxed(svsp, init2vals, INIT2VALS);
1263 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
1268 svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
1269 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
1270 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
1279 static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1283 struct svs_bank *svsb = &svsp->banks[bank_idx];
1287 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1290 static inline void svs_error_isr_handler(struct svs_platform *svsp,
1293 struct svs_bank *svsb = &svsp->banks[bank_idx];
1296 __func__, svs_readl_relaxed(svsp, CORESEL));
1298 svs_readl_relaxed(svsp, SVSEN),
1299 svs_readl_relaxed(svsp, INTSTS));
1301 svs_readl_relaxed(svsp, SMSTATE0),
1302 svs_readl_relaxed(svsp, SMSTATE1));
1303 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1305 svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR);
1308 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1309 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1312 static inline void svs_init01_isr_handler(struct svs_platform *svsp,
1315 struct svs_bank *svsb = &svsp->banks[bank_idx];
1319 __func__, svs_readl_relaxed(svsp, VDESIGN74),
1320 svs_readl_relaxed(svsp, VDESIGN30),
1321 svs_readl_relaxed(svsp, DCVALUES));
1323 svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01);
1326 val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1;
1333 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1336 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1337 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1341 static inline void svs_init02_isr_handler(struct svs_platform *svsp,
1344 struct svs_bank *svsb = &svsp->banks[bank_idx];
1348 __func__, svs_readl_relaxed(svsp, VOP74),
1349 svs_readl_relaxed(svsp, VOP30),
1350 svs_readl_relaxed(svsp, DCVALUES));
1352 svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02);
1355 bdata->get_volts(svsp, svsb);
1357 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1358 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1361 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp,
1364 struct svs_bank *svsb = &svsp->banks[bank_idx];
1367 svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON);
1370 bdata->get_volts(svsp, svsb);
1372 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1373 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
1378 struct svs_platform *svsp = data;
1384 for (idx = 0; idx < svsp->bank_max; idx++) {
1385 svsb = &svsp->banks[idx];
1392 if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) {
1397 svs_switch_bank(svsp, svsb);
1398 int_sts = svs_readl_relaxed(svsp, INTSTS);
1399 svs_en = svs_readl_relaxed(svsp, SVSEN);
1403 svs_init01_isr_handler(svsp, idx);
1406 svs_init02_isr_handler(svsp, idx);
1408 svs_mon_mode_isr_handler(svsp, idx);
1410 svs_error_isr_handler(svsp, idx);
1425 static bool svs_mode_available(struct svs_platform *svsp, u8 mode)
1429 for (i = 0; i < svsp->bank_max; i++)
1430 if (svsp->banks[i].mode_support & mode)
1435 static int svs_init01(struct svs_platform *svsp)
1444 if (!svs_mode_available(svsp, SVSB_MODE_INIT01))
1451 for (idx = 0; idx < svsp->bank_max; idx++) {
1452 svsb = &svsp->banks[idx];
1489 for (idx = 0; idx < svsp->bank_max; idx++) {
1490 svsb = &svsp->banks[idx];
1535 for (idx = 0; idx < svsp->bank_max; idx++) {
1536 svsb = &svsp->banks[idx];
1556 svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01);
1569 for (idx = 0; idx < svsp->bank_max; idx++) {
1570 svsb = &svsp->banks[idx];
1611 static int svs_init02(struct svs_platform *svsp)
1619 if (!svs_mode_available(svsp, SVSB_MODE_INIT02))
1622 for (idx = 0; idx < svsp->bank_max; idx++) {
1623 svsb = &svsp->banks[idx];
1630 svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02);
1647 for (idx = 0; idx < svsp->bank_max; idx++) {
1648 svsb = &svsp->banks[idx];
1666 for (idx = 0; idx < svsp->bank_max; idx++) {
1667 svsb = &svsp->banks[idx];
1668 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1674 static void svs_mon_mode(struct svs_platform *svsp)
1680 for (idx = 0; idx < svsp->bank_max; idx++) {
1681 svsb = &svsp->banks[idx];
1687 svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON);
1692 static int svs_start(struct svs_platform *svsp)
1696 ret = svs_init01(svsp);
1700 ret = svs_init02(svsp);
1704 svs_mon_mode(svsp);
1711 struct svs_platform *svsp = dev_get_drvdata(dev);
1715 for (idx = 0; idx < svsp->bank_max; idx++) {
1716 struct svs_bank *svsb = &svsp->banks[idx];
1718 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1721 ret = reset_control_assert(svsp->rst);
1723 dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1727 clk_disable_unprepare(svsp->main_clk);
1734 struct svs_platform *svsp = dev_get_drvdata(dev);
1737 ret = clk_prepare_enable(svsp->main_clk);
1739 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1743 ret = reset_control_deassert(svsp->rst);
1745 dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1749 ret = svs_init02(svsp);
1753 svs_mon_mode(svsp);
1758 dev_err(svsp->dev, "assert reset: %d\n",
1759 reset_control_assert(svsp->rst));
1762 clk_disable_unprepare(svsp->main_clk);
1766 static int svs_bank_resource_setup(struct svs_platform *svsp)
1776 dev_set_drvdata(svsp->dev, svsp);
1778 for (idx = 0; idx < svsp->bank_max; idx++) {
1779 svsb = &svsp->banks[idx];
1787 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL);
1791 svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s",
1801 dev_set_drvdata(svsb->dev, svsp);
1860 static int svs_get_efuse_data(struct svs_platform *svsp,
1866 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name);
1868 dev_err(svsp->dev, "no \"%s\"? %ld\n",
1898 static bool svs_is_available(struct svs_platform *svsp)
1903 for (i = 0; i < svsp->efuse_max; i++) {
1904 if (svsp->efuse[i])
1914 static bool svs_common_parse_efuse(struct svs_platform *svsp,
1923 if (!svs_is_available(svsp))
1927 val = svs_get_fuse_val(svsp->tefuse, &tfm, 8);
1933 ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8);
1934 vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2);
1936 for (i = 0; i < svsp->bank_max; i++) {
1937 struct svs_bank *svsb = &svsp->banks[i];
1947 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1948 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1949 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1950 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1951 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1954 svsb->mts = (svsp->ts_coeff * 2) / 1000;
1955 svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4;
1961 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp,
1971 for (i = 0; i < svsp->efuse_max; i++)
1972 if (svsp->efuse[i])
1973 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1974 i, svsp->efuse[i]);
1976 if (!svsp->efuse[2]) {
1977 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1982 ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4);
1984 for (idx = 0; idx < svsp->bank_max; idx++) {
1985 svsb = &svsp->banks[idx];
1992 svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1993 svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1994 svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1995 svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1996 svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
2025 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
2026 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
2028 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
2029 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
2030 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
2031 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
2032 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
2033 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
2035 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
2036 adc_cali_en_t = svsp->tefuse[0] & BIT(0);
2037 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
2039 ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
2043 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
2060 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
2081 for (idx = 0; idx < svsp->bank_max; idx++) {
2082 svsb = &svsp->banks[idx];
2115 for (idx = 0; idx < svsp->bank_max; idx++) {
2116 svsb = &svsp->banks[idx];
2123 static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2131 dev_err(svsp->dev, "cannot find %s node\n", node_name);
2138 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2145 static struct device *svs_add_device_link(struct svs_platform *svsp,
2151 dev = svs_get_subsys_device(svsp, node_name);
2155 sup_link = device_link_add(svsp->dev, dev,
2158 dev_err(svsp->dev, "sup_link is NULL\n");
2168 static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2173 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2174 if (IS_ERR(svsp->rst))
2175 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2178 dev = svs_add_device_link(svsp, "thermal-sensor");
2180 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2183 for (idx = 0; idx < svsp->bank_max; idx++) {
2184 struct svs_bank *svsb = &svsp->banks[idx];
2193 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2197 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2199 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2207 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2215 static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2220 dev = svs_add_device_link(svsp, "thermal-sensor");
2222 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2225 for (idx = 0; idx < svsp->bank_max; idx++) {
2226 struct svs_bank *svsb = &svsp->banks[idx];
2235 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2238 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2246 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2819 struct svs_platform *svsp;
2825 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2826 if (!svsp)
2829 svsp->dev = &pdev->dev;
2830 svsp->banks = svsp_data->banks;
2831 svsp->regs = svsp_data->regs;
2832 svsp->bank_max = svsp_data->bank_max;
2833 svsp->ts_coeff = svsp_data->ts_coeff;
2835 ret = svsp_data->probe(svsp);
2839 ret = svs_get_efuse_data(svsp, "svs-calibration-data",
2840 &svsp->efuse, &svsp->efuse_max);
2844 ret = svs_get_efuse_data(svsp, "t-calibration-data",
2845 &svsp->tefuse, &svsp->tefuse_max);
2851 if (!svsp_data->efuse_parsing(svsp, svsp_data)) {
2852 ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n");
2856 ret = svs_bank_resource_setup(svsp);
2858 dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n");
2868 svsp->main_clk = devm_clk_get(svsp->dev, "main");
2869 if (IS_ERR(svsp->main_clk)) {
2870 ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk),
2875 ret = clk_prepare_enable(svsp->main_clk);
2877 dev_err_probe(svsp->dev, ret, "cannot enable main clk\n");
2881 svsp->base = of_iomap(svsp->dev->of_node, 0);
2882 if (IS_ERR_OR_NULL(svsp->base)) {
2883 ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n");
2887 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2888 IRQF_ONESHOT, svsp_data->name, svsp);
2890 dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq);
2894 ret = svs_start(svsp);
2896 dev_err_probe(svsp->dev, ret, "svs start fail\n");
2901 ret = svs_create_debug_cmds(svsp);
2903 dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n");
2911 iounmap(svsp->base);
2913 clk_disable_unprepare(svsp->main_clk);
2915 kfree(svsp->tefuse);
2917 kfree(svsp->efuse);