Lines Matching +full:sp +full:- +full:disabled +full:- +full:ports
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
71 "beginning. Default is 0 - class 2 not supported.");
83 "a PORT-DOWN status.");
90 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
102 "vary by ISP type. Default is 1 - allocate memory.");
109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
120 "\t\t0x1e400000 - Preferred value for capturing essential "
141 "0 - no FDMI registrations. "
142 "1 - provide FDMI registrations (default).");
154 " Enable T10-CRC-DIF:\n"
156 " 0 -- No DIF Support\n"
157 " 1 -- Enable DIF for all types\n"
158 " 2 -- Enable DIF for all types, except Type 0.\n");
168 "0 - no NVMe. Default is Y");
173 " Enable T10-CRC-DIF Error isolation by HBA:\n"
175 " 0 -- Error isolation disabled\n"
176 " 1 -- Error isolation enabled only for DIX Type 0\n"
177 " 2 -- Error isolation enabled for all Types\n");
191 " 2 -- load firmware via the request_firmware() (hotplug).\n"
193 " 1 -- load firmware from flash.\n"
194 " 0 -- use default semantics.\n");
200 " 0 -- Regular doorbell.\n"
201 " 1 -- CAMRAM doorbell (faster).\n");
207 "Default is 0 - Do not use GFF_ID information.");
213 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
219 " 0 (Default) -- Reset on failure.\n"
220 " 1 -- Do not reset on failure.\n");
232 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
238 "0 - MiniDump disabled. "
239 "1 (Default) - MiniDump enabled.");
245 "0 (Default)- Disabled.");
262 "1 - Set fw option to hold ABTS.");
269 "1 - Move IOCBs.");
280 "Set to enable MSI or MSI-X interrupt mechanism.\n"
281 " Default is 1, enable MSI-X interrupt mechanism.\n"
282 " 0 -- enable traditional pin-based mechanism.\n"
283 " 1 -- enable MSI-X interrupt mechanism.\n"
284 " 2 -- enable MSI interrupt mechanism.\n");
290 " 0 (default): disabled");
302 " 0 -- Let HBA firmware decide\n"
303 " 1 -- Force T10 CRC\n"
304 " 2 -- Force IP checksum\n");
318 " Default is 0 - No SmartSAN registration,"
319 " 1 - Register SmartSAN Management Attributes.");
326 "0 - no RDP responses (default). "
327 "1 - provide RDP responses.");
337 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
349 "1 - Minimum number of queues supported\n"
350 "8 - Default value");
356 "0 - FC2 Target support is disabled. "
357 "1 - FC2 Target support is enabled (default).");
370 timer_setup(&vha->timer, qla2x00_timer, 0);
371 vha->timer.expires = jiffies + interval * HZ;
372 add_timer(&vha->timer);
373 vha->timer_active = 1;
380 if (vha->device_flags & DFLG_DEV_FAILED) {
386 mod_timer(&vha->timer, jiffies + interval * HZ);
392 timer_delete_sync(&vha->timer);
393 vha->timer_active = 0;
407 /* -------------------------------------------------------------------------- */
411 struct qla_hw_data *ha = vha->hw;
413 rsp->qpair = ha->base_qpair;
414 rsp->req = req;
415 ha->base_qpair->hw = ha;
416 ha->base_qpair->req = req;
417 ha->base_qpair->rsp = rsp;
418 ha->base_qpair->vha = vha;
419 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
420 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
421 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
422 ha->base_qpair->srb_mempool = ha->srb_mempool;
423 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
424 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
425 ha->base_qpair->enable_class_2 = ql2xenableclass2;
427 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
428 ha->base_qpair->pdev = ha->pdev;
431 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
437 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
439 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
441 if (!ha->req_q_map) {
447 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
449 if (!ha->rsp_q_map) {
455 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
456 if (ha->base_qpair == NULL) {
464 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
465 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
467 if (!ha->queue_pair_map) {
473 kfree(ha->queue_pair_map);
474 ha->queue_pair_map = NULL;
483 ha->rsp_q_map[0] = rsp;
484 ha->req_q_map[0] = req;
485 set_bit(0, ha->rsp_qid_map);
486 set_bit(0, ha->req_qid_map);
490 kfree(ha->base_qpair);
491 ha->base_qpair = NULL;
493 kfree(ha->rsp_q_map);
494 ha->rsp_q_map = NULL;
496 kfree(ha->req_q_map);
497 ha->req_q_map = NULL;
499 return -ENOMEM;
505 if (req && req->ring_fx00)
506 dma_free_coherent(&ha->pdev->dev,
507 (req->length_fx00 + 1) * sizeof(request_t),
508 req->ring_fx00, req->dma_fx00);
509 } else if (req && req->ring)
510 dma_free_coherent(&ha->pdev->dev,
511 (req->length + 1) * sizeof(request_t),
512 req->ring, req->dma);
515 kfree(req->outstanding_cmds);
523 if (rsp && rsp->ring_fx00)
524 dma_free_coherent(&ha->pdev->dev,
525 (rsp->length_fx00 + 1) * sizeof(request_t),
526 rsp->ring_fx00, rsp->dma_fx00);
527 } else if (rsp && rsp->ring) {
528 dma_free_coherent(&ha->pdev->dev,
529 (rsp->length + 1) * sizeof(response_t),
530 rsp->ring, rsp->dma);
542 if (ha->queue_pair_map) {
543 kfree(ha->queue_pair_map);
544 ha->queue_pair_map = NULL;
546 if (ha->base_qpair) {
547 kfree(ha->base_qpair);
548 ha->base_qpair = NULL;
552 spin_lock_irqsave(&ha->hardware_lock, flags);
553 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
554 if (!test_bit(cnt, ha->req_qid_map))
557 req = ha->req_q_map[cnt];
558 clear_bit(cnt, ha->req_qid_map);
559 ha->req_q_map[cnt] = NULL;
561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
563 spin_lock_irqsave(&ha->hardware_lock, flags);
565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
567 kfree(ha->req_q_map);
568 ha->req_q_map = NULL;
571 spin_lock_irqsave(&ha->hardware_lock, flags);
572 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
573 if (!test_bit(cnt, ha->rsp_qid_map))
576 rsp = ha->rsp_q_map[cnt];
577 clear_bit(cnt, ha->rsp_qid_map);
578 ha->rsp_q_map[cnt] = NULL;
579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
581 spin_lock_irqsave(&ha->hardware_lock, flags);
583 spin_unlock_irqrestore(&ha->hardware_lock, flags);
585 kfree(ha->rsp_q_map);
586 ha->rsp_q_map = NULL;
592 struct qla_hw_data *ha = vha->hw;
598 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
600 snprintf(str, str_len, "PCI-X (%s MHz)",
603 pci_bus = (ha->pci_attr & BIT_8) >> 8;
616 struct qla_hw_data *ha = vha->hw;
619 if (pci_is_pcie(ha->pdev)) {
623 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
649 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
654 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
665 struct qla_hw_data *ha = vha->hw;
667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
668 ha->fw_minor_version, ha->fw_subminor_version);
670 if (ha->fw_attributes & BIT_9) {
675 switch (ha->fw_attributes & 0xFF) {
689 sprintf(un_str, "(%x)", ha->fw_attributes);
693 if (ha->fw_attributes & 0x100)
702 struct qla_hw_data *ha = vha->hw;
704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
709 void qla2x00_sp_free_dma(srb_t *sp)
711 struct qla_hw_data *ha = sp->vha->hw;
712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
714 if (sp->flags & SRB_DMA_VALID) {
716 sp->flags &= ~SRB_DMA_VALID;
719 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
720 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
721 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
722 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
725 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
727 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
728 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
731 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
732 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
734 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
735 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
738 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
739 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
741 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
742 ctx1->fcp_cmnd_dma);
743 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
744 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
745 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
748 if (sp->flags & SRB_GOT_BUF)
749 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
752 void qla2x00_sp_compl(srb_t *sp, int res)
754 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
755 struct completion *comp = sp->comp;
758 kref_put(&sp->cmd_kref, qla2x00_sp_release);
759 cmd->result = res;
760 sp->type = 0;
766 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
768 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
769 struct qla_hw_data *ha = sp->fcport->vha->hw;
771 if (sp->flags & SRB_DMA_VALID) {
773 sp->flags &= ~SRB_DMA_VALID;
776 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
777 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
778 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
779 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
784 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
788 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
789 struct crc_context *difctx = sp->u.scmd.crc_ctx;
793 &difctx->ldif_dma_hndl_list, list) {
794 list_del(&dif_dsd->list);
795 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
796 dif_dsd->dsd_list_dma);
798 difctx->no_dif_bundl--;
802 &difctx->ldif_dsd_list, list) {
803 list_del(&dif_dsd->list);
804 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
805 dif_dsd->dsd_list_dma);
807 difctx->no_ldif_dsd--;
810 if (difctx->no_ldif_dsd) {
811 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
812 "%s: difctx->no_ldif_dsd=%x\n",
813 __func__, difctx->no_ldif_dsd);
816 if (difctx->no_dif_bundl) {
817 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
818 "%s: difctx->no_dif_bundl=%x\n",
819 __func__, difctx->no_dif_bundl);
821 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
824 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
825 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
827 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
828 ctx1->fcp_cmnd_dma);
829 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
830 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
831 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
832 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
835 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
836 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
838 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
839 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
842 if (sp->flags & SRB_GOT_BUF)
843 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
846 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
848 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
849 struct completion *comp = sp->comp;
852 kref_put(&sp->cmd_kref, qla2x00_sp_release);
853 cmd->result = res;
854 sp->type = 0;
864 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
865 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
866 struct qla_hw_data *ha = vha->hw;
867 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
868 srb_t *sp;
871 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
873 cmd->result = DID_NO_CONNECT << 16;
877 if (ha->mqenable) {
884 qpair = ha->queue_pair_map[hwq];
890 if (ha->flags.eeh_busy) {
891 if (ha->flags.pci_channel_io_perm_failure) {
895 cmd->result = DID_NO_CONNECT << 16;
899 cmd->result = DID_REQUEUE << 16;
906 cmd->result = rval;
913 if (!vha->flags.difdix_supported &&
918 cmd->result = DID_NO_CONNECT << 16;
922 if (!fcport || fcport->deleted) {
923 cmd->result = DID_IMM_RETRY << 16;
927 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
928 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
929 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
932 atomic_read(&fcport->state),
933 atomic_read(&base_vha->loop_state));
934 cmd->result = DID_NO_CONNECT << 16;
941 * Return target busy if we've received a non-zero retry_delay_timer
944 if (fcport->retry_delay_timestamp == 0) {
946 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
947 fcport->retry_delay_timestamp = 0;
951 sp = scsi_cmd_priv(cmd);
953 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
955 sp->u.scmd.cmd = cmd;
956 sp->type = SRB_SCSI_CMD;
957 sp->free = qla2x00_sp_free_dma;
958 sp->done = qla2x00_sp_compl;
960 rval = ha->isp_ops->start_scsi(sp);
971 kref_put(&sp->cmd_kref, qla2x00_sp_release);
988 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
989 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
990 struct qla_hw_data *ha = vha->hw;
991 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
992 srb_t *sp;
997 cmd->result = rval;
1004 if (!qpair->online) {
1006 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1007 cmd->result = DID_NO_CONNECT << 16;
1011 if (!fcport || fcport->deleted) {
1012 cmd->result = DID_IMM_RETRY << 16;
1016 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1017 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1018 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1021 atomic_read(&fcport->state),
1022 atomic_read(&base_vha->loop_state));
1023 cmd->result = DID_NO_CONNECT << 16;
1030 * Return target busy if we've received a non-zero retry_delay_timer
1033 if (fcport->retry_delay_timestamp == 0) {
1035 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1036 fcport->retry_delay_timestamp = 0;
1040 sp = scsi_cmd_priv(cmd);
1042 qla2xxx_init_sp(sp, vha, qpair, fcport);
1044 sp->u.scmd.cmd = cmd;
1045 sp->type = SRB_SCSI_CMD;
1046 sp->free = qla2xxx_qpair_sp_free_dma;
1047 sp->done = qla2xxx_qpair_sp_compl;
1049 rval = ha->isp_ops->start_scsi_mq(sp);
1060 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1075 * finally HBA is disabled ie marked offline
1078 * ha - pointer to host adapter structure
1081 * Does context switching-Release SPIN_LOCK
1086 * Failed (Adapter is offline/disabled) : 1
1093 struct qla_hw_data *ha = vha->hw;
1094 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1097 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1098 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1099 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1100 ha->dpc_active) && time_before(jiffies, wait_online)) {
1104 if (base_vha->flags.online)
1114 struct qla_hw_data *ha = vha->hw;
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1122 vha, vha->fcport_count);
1123 res = (vha->fcport_count == 0);
1127 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1128 if (fcport->deleted != QLA_SESS_DELETED) {
1139 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1156 if (wait_event_timeout(vha->fcport_waitQ,
1161 flush_workqueue(vha->hw->wq);
1169 * ha - pointer to host adapter structure
1172 * Does context switching-Release SPIN_LOCK
1179 struct qla_hw_data *ha = vha->hw;
1180 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1182 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1183 ha->flags.mbox_busy) ||
1184 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1185 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1186 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1197 struct qla_hw_data *ha = vha->hw;
1198 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1201 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1202 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1203 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1204 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1208 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1209 ha->flags.chip_reset_done)
1212 if (ha->flags.chip_reset_done)
1238 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1240 srb_t *sp;
1245 struct qla_hw_data *ha = vha->hw;
1263 sp = scsi_cmd_priv(cmd);
1264 qpair = sp->qpair;
1266 vha->cmd_timeout_cnt++;
1268 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1271 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1272 sp->comp = ∁
1273 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1276 id = cmd->device->id;
1277 lun = cmd->device->lun;
1280 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1281 vha->host_no, id, lun, sp, cmd, sp->handle);
1284 * Abort will release the original Command/sp from FW. Let the
1288 rval = ha->isp_ops->abort_command(sp);
1294 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1301 __func__, ha->r_a_tov/10);
1312 sp->comp = NULL;
1315 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1316 vha->host_no, id, lun, ret);
1333 scsi_qla_host_t *vha = qpair->vha;
1334 struct req_que *req = qpair->req;
1335 srb_t *sp;
1339 struct qla_hw_data *ha = vha->hw;
1343 while (wait_iter--) {
1346 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1347 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1348 sp = req->outstanding_cmds[cnt];
1349 if (!sp)
1351 if (sp->type != SRB_SCSI_CMD)
1353 if (vha->vp_idx != sp->vha->vp_idx)
1356 cmd = GET_CMD_SP(sp);
1362 if (sp->fcport)
1363 match = sp->fcport->d_id.b24 == t;
1368 if (sp->fcport)
1369 match = (sp->fcport->d_id.b24 == t &&
1370 cmd->device->lun == l);
1378 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1380 if (unlikely(pci_channel_offline(ha->pdev)) ||
1381 ha->flags.eeh_busy) {
1393 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1396 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1402 if (wait_iter == -1)
1413 struct qla_hw_data *ha = vha->hw;
1416 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1418 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1419 qpair = ha->queue_pair_map[i];
1438 struct scsi_device *sdev = cmd->device;
1439 scsi_qla_host_t *vha = shost_priv(sdev->host);
1441 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1442 struct qla_hw_data *ha = vha->hw;
1460 if (fcport->deleted)
1464 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1465 sdev->id, sdev->lun, cmd);
1474 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1481 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1482 cmd->device->lun,
1491 vha->host_no, sdev->id, sdev->lun, cmd);
1498 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1500 vha->reset_cmd_err_cnt++;
1507 struct scsi_device *sdev = cmd->device;
1510 struct qla_hw_data *ha = vha->hw;
1511 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1529 if (fcport->deleted)
1533 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1534 sdev->id, cmd);
1543 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1549 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1558 vha->host_no, sdev->id, cmd);
1565 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1567 vha->reset_cmd_err_cnt++;
1589 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1593 struct qla_hw_data *ha = vha->hw;
1602 id = cmd->device->id;
1603 lun = cmd->device->lun;
1609 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1613 "Wait for hba online failed board disabled.\n");
1634 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1657 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1658 struct qla_hw_data *ha = vha->hw;
1662 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1671 id = cmd->device->id;
1672 lun = cmd->device->lun;
1675 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1681 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1688 if (IS_P3P_TYPE(vha->hw)) {
1696 if (ha->wq)
1697 flush_workqueue(ha->wq);
1699 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1700 if (ha->isp_ops->abort_isp(base_vha)) {
1701 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1703 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1711 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1722 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1741 struct qla_hw_data *ha = vha->hw;
1746 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1747 atomic_set(&vha->loop_state, LOOP_DOWN);
1748 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1757 if (ha->flags.enable_lip_reset) {
1765 vha->marker_needed = 1;
1774 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1776 __releases(qp->qp_lock_ptr)
1777 __acquires(qp->qp_lock_ptr)
1780 scsi_qla_host_t *vha = qp->vha;
1781 struct qla_hw_data *ha = vha->hw;
1782 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1787 lockdep_assert_held(qp->qp_lock_ptr);
1790 sp->done(sp, res);
1794 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1795 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1796 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1798 if (sp->comp) {
1799 sp->done(sp, res);
1803 sp->comp = ∁
1804 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1806 rval = ha->isp_ops->abort_command(sp);
1809 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1816 __func__, ha->r_a_tov/10);
1819 /* else FW return SP to driver */
1826 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1827 switch (sp->type) {
1830 sp->done(sp, res);
1834 sp->done(sp, res);
1838 sp->done(sp, res);
1851 srb_t *sp;
1852 scsi_qla_host_t *vha = qp->vha;
1853 struct qla_hw_data *ha = vha->hw;
1855 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1858 if (!ha->req_q_map)
1860 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1861 req = qp->req;
1862 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1863 sp = req->outstanding_cmds[cnt];
1864 if (sp) {
1866 req->outstanding_cmds[cnt] = NULL;
1867 sp->done(sp, res);
1871 switch (sp->cmd_type) {
1873 qla2x00_abort_srb(qp, sp, res, &flags);
1876 if (!vha->hw->tgt.tgt_ops || !tgt ||
1879 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1880 vha->dpc_flags);
1883 cmd = (struct qla_tgt_cmd *)sp;
1884 cmd->aborted = 1;
1892 req->outstanding_cmds[cnt] = NULL;
1895 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1906 struct qla_hw_data *ha = vha->hw;
1909 if (!ha->base_qpair)
1911 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1913 if (!ha->queue_pair_map)
1915 for (que = 0; que < ha->max_qpairs; que++) {
1916 if (!ha->queue_pair_map[que])
1919 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1929 return -ENXIO;
1931 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1939 scsi_qla_host_t *vha = shost_priv(sdev->host);
1940 struct req_que *req = vha->req;
1942 scsi_change_queue_depth(sdev, req->max_q_depth);
1949 sdev->hostdata = NULL;
1953 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1963 ha->flags.enable_64bit_addressing = 0;
1965 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1966 /* Any upper-dword bits set? */
1967 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1968 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1970 ha->flags.enable_64bit_addressing = 1;
1971 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1972 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1977 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1978 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1985 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1987 spin_lock_irqsave(&ha->hardware_lock, flags);
1988 ha->interrupts_on = 1;
1990 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1991 rd_reg_word(®->ictrl);
1992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2000 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2002 spin_lock_irqsave(&ha->hardware_lock, flags);
2003 ha->interrupts_on = 0;
2005 wrt_reg_word(®->ictrl, 0);
2006 rd_reg_word(®->ictrl);
2007 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2016 spin_lock_irqsave(&ha->hardware_lock, flags);
2017 ha->interrupts_on = 1;
2018 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2019 rd_reg_dword(®->ictrl);
2020 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2031 spin_lock_irqsave(&ha->hardware_lock, flags);
2032 ha->interrupts_on = 0;
2033 wrt_reg_dword(®->ictrl, 0);
2034 rd_reg_dword(®->ictrl);
2035 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2044 if (pci_request_selected_regions(ha->pdev, ha->bars,
2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2048 pci_name(ha->pdev));
2051 if (!(ha->bars & 1))
2055 pio = pci_resource_start(ha->pdev, 0);
2056 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2057 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2058 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2060 pci_name(ha->pdev));
2064 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2066 pci_name(ha->pdev));
2069 ha->pio_address = pio;
2070 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2072 (unsigned long long)ha->pio_address);
2076 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2077 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2079 pci_name(ha->pdev));
2082 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2085 pci_name(ha->pdev));
2089 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2090 if (!ha->iobase) {
2091 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2093 pci_name(ha->pdev));
2098 ha->max_req_queues = ha->max_rsp_queues = 1;
2099 ha->msix_count = QLA_BASE_VECTORS;
2102 if (!(ha->fw_attributes & BIT_6))
2109 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2110 pci_resource_len(ha->pdev, 3));
2111 if (ha->mqiobase) {
2112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2113 "MQIO Base=%p.\n", ha->mqiobase);
2115 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2116 ha->msix_count = msix + 1;
2119 ha->max_req_queues = ha->msix_count - 1;
2120 ha->max_rsp_queues = ha->max_req_queues;
2122 ha->max_qpairs = ha->max_rsp_queues - 1;
2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2124 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2126 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2127 "MSI-X vector count: %d.\n", ha->msix_count);
2129 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2134 "MSIX Count: %d.\n", ha->msix_count);
2138 return (-ENOMEM);
2147 if (pci_request_selected_regions(ha->pdev, ha->bars,
2149 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2151 pci_name(ha->pdev));
2157 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2158 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2160 pci_name(ha->pdev));
2163 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2164 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2166 pci_name(ha->pdev));
2170 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2171 if (!ha->iobase) {
2172 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2174 pci_name(ha->pdev));
2178 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2180 * - mbar 2, a.k.a region 4 */
2181 ha->max_req_queues = ha->max_rsp_queues = 1;
2182 ha->msix_count = QLA_BASE_VECTORS;
2183 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2184 pci_resource_len(ha->pdev, 4));
2186 if (!ha->mqiobase) {
2187 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2192 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2193 pci_resource_len(ha->pdev, 2));
2194 if (ha->msixbase) {
2196 pci_read_config_word(ha->pdev,
2198 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2205 ha->max_req_queues = ha->msix_count - 1;
2209 ha->max_req_queues--;
2211 ha->max_rsp_queues = ha->max_req_queues;
2215 ha->max_qpairs = ha->max_req_queues - 1;
2216 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2217 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2219 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2220 "MSI-X vector count: %d.\n", ha->msix_count);
2222 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2227 "MSIX Count: %d.\n", ha->msix_count);
2231 return -ENOMEM;
2628 ha->device_type = DT_EXTENDED_IDS;
2629 switch (ha->pdev->device) {
2631 ha->isp_type |= DT_ISP2100;
2632 ha->device_type &= ~DT_EXTENDED_IDS;
2633 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2636 ha->isp_type |= DT_ISP2200;
2637 ha->device_type &= ~DT_EXTENDED_IDS;
2638 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2641 ha->isp_type |= DT_ISP2300;
2642 ha->device_type |= DT_ZIO_SUPPORTED;
2643 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2646 ha->isp_type |= DT_ISP2312;
2647 ha->device_type |= DT_ZIO_SUPPORTED;
2648 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2651 ha->isp_type |= DT_ISP2322;
2652 ha->device_type |= DT_ZIO_SUPPORTED;
2653 if (ha->pdev->subsystem_vendor == 0x1028 &&
2654 ha->pdev->subsystem_device == 0x0170)
2655 ha->device_type |= DT_OEM_001;
2656 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2659 ha->isp_type |= DT_ISP6312;
2660 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2663 ha->isp_type |= DT_ISP6322;
2664 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2667 ha->isp_type |= DT_ISP2422;
2668 ha->device_type |= DT_ZIO_SUPPORTED;
2669 ha->device_type |= DT_FWI2;
2670 ha->device_type |= DT_IIDMA;
2671 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2674 ha->isp_type |= DT_ISP2432;
2675 ha->device_type |= DT_ZIO_SUPPORTED;
2676 ha->device_type |= DT_FWI2;
2677 ha->device_type |= DT_IIDMA;
2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2681 ha->isp_type |= DT_ISP8432;
2682 ha->device_type |= DT_ZIO_SUPPORTED;
2683 ha->device_type |= DT_FWI2;
2684 ha->device_type |= DT_IIDMA;
2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2688 ha->isp_type |= DT_ISP5422;
2689 ha->device_type |= DT_FWI2;
2690 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2693 ha->isp_type |= DT_ISP5432;
2694 ha->device_type |= DT_FWI2;
2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2698 ha->isp_type |= DT_ISP2532;
2699 ha->device_type |= DT_ZIO_SUPPORTED;
2700 ha->device_type |= DT_FWI2;
2701 ha->device_type |= DT_IIDMA;
2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2705 ha->isp_type |= DT_ISP8001;
2706 ha->device_type |= DT_ZIO_SUPPORTED;
2707 ha->device_type |= DT_FWI2;
2708 ha->device_type |= DT_IIDMA;
2709 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2712 ha->isp_type |= DT_ISP8021;
2713 ha->device_type |= DT_ZIO_SUPPORTED;
2714 ha->device_type |= DT_FWI2;
2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2720 ha->isp_type |= DT_ISP8044;
2721 ha->device_type |= DT_ZIO_SUPPORTED;
2722 ha->device_type |= DT_FWI2;
2723 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2728 ha->isp_type |= DT_ISP2031;
2729 ha->device_type |= DT_ZIO_SUPPORTED;
2730 ha->device_type |= DT_FWI2;
2731 ha->device_type |= DT_IIDMA;
2732 ha->device_type |= DT_T10_PI;
2733 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2736 ha->isp_type |= DT_ISP8031;
2737 ha->device_type |= DT_ZIO_SUPPORTED;
2738 ha->device_type |= DT_FWI2;
2739 ha->device_type |= DT_IIDMA;
2740 ha->device_type |= DT_T10_PI;
2741 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2744 ha->isp_type |= DT_ISPFX00;
2747 ha->isp_type |= DT_ISP2071;
2748 ha->device_type |= DT_ZIO_SUPPORTED;
2749 ha->device_type |= DT_FWI2;
2750 ha->device_type |= DT_IIDMA;
2751 ha->device_type |= DT_T10_PI;
2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2755 ha->isp_type |= DT_ISP2271;
2756 ha->device_type |= DT_ZIO_SUPPORTED;
2757 ha->device_type |= DT_FWI2;
2758 ha->device_type |= DT_IIDMA;
2759 ha->device_type |= DT_T10_PI;
2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2763 ha->isp_type |= DT_ISP2261;
2764 ha->device_type |= DT_ZIO_SUPPORTED;
2765 ha->device_type |= DT_FWI2;
2766 ha->device_type |= DT_IIDMA;
2767 ha->device_type |= DT_T10_PI;
2768 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2772 ha->isp_type |= DT_ISP2081;
2773 ha->device_type |= DT_ZIO_SUPPORTED;
2774 ha->device_type |= DT_FWI2;
2775 ha->device_type |= DT_IIDMA;
2776 ha->device_type |= DT_T10_PI;
2777 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2781 ha->isp_type |= DT_ISP2281;
2782 ha->device_type |= DT_ZIO_SUPPORTED;
2783 ha->device_type |= DT_FWI2;
2784 ha->device_type |= DT_IIDMA;
2785 ha->device_type |= DT_T10_PI;
2786 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2791 ha->port_no = ha->portnum & 1;
2794 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2797 ha->port_no--;
2799 ha->port_no = !(ha->port_no & 1);
2802 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2804 ha->device_type, ha->port_no, ha->fw_srisc_address);
2812 if (vha->hw->flags.running_gold_fw)
2815 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2816 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2817 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2818 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2826 if (test_bit(UNLOADING, &vha->dpc_flags))
2828 if (!vha->host)
2830 if (time > vha->hw->loop_reset_delay * HZ)
2833 return atomic_read(&vha->loop_state) == LOOP_READY;
2840 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2842 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2850 struct qla_hw_data *ha = vha->hw;
2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2855 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2858 while (!list_empty(&vha->work_list) && i > 0) {
2860 i--;
2863 spin_lock_irqsave(&vha->work_lock, flags);
2864 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2865 spin_unlock_irqrestore(&vha->work_lock, flags);
2874 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2895 int ret = -ENODEV;
2910 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2911 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2912 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2913 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2914 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2915 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2916 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2917 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2918 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2919 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2920 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2958 ha->pdev = pdev;
2959 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2960 spin_lock_init(&ha->tgt.q_full_lock);
2961 spin_lock_init(&ha->tgt.sess_lock);
2962 spin_lock_init(&ha->tgt.atio_lock);
2964 spin_lock_init(&ha->sadb_lock);
2965 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2966 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2968 spin_lock_init(&ha->sadb_fp_lock);
2975 atomic_set(&ha->nvme_active_aen_cnt, 0);
2978 ha->bars = bars;
2979 ha->mem_only = mem_only;
2980 spin_lock_init(&ha->hardware_lock);
2981 spin_lock_init(&ha->vport_slock);
2982 mutex_init(&ha->selflogin_lock);
2983 mutex_init(&ha->optrom_mutex);
2985 /* Set ISP-type information. */
2991 pdev->needs_freset = 1;
2993 ha->prev_topology = 0;
2994 ha->init_cb_size = sizeof(init_cb_t);
2995 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2996 ha->optrom_size = OPTROM_SIZE_2300;
2997 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2998 atomic_set(&ha->num_pend_mbx_stage1, 0);
2999 atomic_set(&ha->num_pend_mbx_stage2, 0);
3000 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3001 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3002 INIT_LIST_HEAD(&ha->tmf_pending);
3003 INIT_LIST_HEAD(&ha->tmf_active);
3007 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3008 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3011 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3012 ha->gid_list_info_size = 4;
3013 ha->flash_conf_off = ~0;
3014 ha->flash_data_off = ~0;
3015 ha->nvram_conf_off = ~0;
3016 ha->nvram_data_off = ~0;
3017 ha->isp_ops = &qla2100_isp_ops;
3019 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3020 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3023 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3024 ha->gid_list_info_size = 4;
3025 ha->flash_conf_off = ~0;
3026 ha->flash_data_off = ~0;
3027 ha->nvram_conf_off = ~0;
3028 ha->nvram_data_off = ~0;
3029 ha->isp_ops = &qla2100_isp_ops;
3031 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3032 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3035 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3036 ha->gid_list_info_size = 6;
3038 ha->optrom_size = OPTROM_SIZE_2322;
3039 ha->flash_conf_off = ~0;
3040 ha->flash_data_off = ~0;
3041 ha->nvram_conf_off = ~0;
3042 ha->nvram_data_off = ~0;
3043 ha->isp_ops = &qla2300_isp_ops;
3045 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3046 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3049 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3050 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3051 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3052 ha->gid_list_info_size = 8;
3053 ha->optrom_size = OPTROM_SIZE_24XX;
3054 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3055 ha->isp_ops = &qla24xx_isp_ops;
3056 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3057 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3058 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3059 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3061 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3062 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3065 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3066 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3067 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3068 ha->gid_list_info_size = 8;
3069 ha->optrom_size = OPTROM_SIZE_25XX;
3070 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3071 ha->isp_ops = &qla25xx_isp_ops;
3072 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3073 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3074 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3075 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3077 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3078 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3081 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3082 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3083 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3084 ha->gid_list_info_size = 8;
3085 ha->optrom_size = OPTROM_SIZE_81XX;
3086 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3087 ha->isp_ops = &qla81xx_isp_ops;
3088 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3089 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3090 ha->nvram_conf_off = ~0;
3091 ha->nvram_data_off = ~0;
3093 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3094 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3097 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3098 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3099 ha->gid_list_info_size = 8;
3100 ha->optrom_size = OPTROM_SIZE_82XX;
3101 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3102 ha->isp_ops = &qla82xx_isp_ops;
3103 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3104 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3105 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3106 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3108 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3109 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3112 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3113 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3114 ha->gid_list_info_size = 8;
3115 ha->optrom_size = OPTROM_SIZE_83XX;
3116 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3117 ha->isp_ops = &qla8044_isp_ops;
3118 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3119 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3120 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3121 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3123 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3124 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3125 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3128 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3129 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3130 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3131 ha->gid_list_info_size = 8;
3132 ha->optrom_size = OPTROM_SIZE_83XX;
3133 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3134 ha->isp_ops = &qla83xx_isp_ops;
3135 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3136 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3137 ha->nvram_conf_off = ~0;
3138 ha->nvram_data_off = ~0;
3140 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3141 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3142 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3145 ha->isp_ops = &qlafx00_isp_ops;
3146 ha->port_down_retry_count = 30; /* default value */
3147 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3148 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3149 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3150 ha->mr.fw_hbt_en = 1;
3151 ha->mr.host_info_resend = false;
3152 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3154 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3155 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3156 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3159 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3160 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3161 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3162 ha->gid_list_info_size = 8;
3163 ha->optrom_size = OPTROM_SIZE_83XX;
3164 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3165 ha->isp_ops = &qla27xx_isp_ops;
3166 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3167 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3168 ha->nvram_conf_off = ~0;
3169 ha->nvram_data_off = ~0;
3171 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3172 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3173 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3176 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3177 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3178 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3179 ha->gid_list_info_size = 8;
3180 ha->optrom_size = OPTROM_SIZE_28XX;
3181 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3182 ha->isp_ops = &qla27xx_isp_ops;
3183 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3184 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3185 ha->nvram_conf_off = ~0;
3186 ha->nvram_data_off = ~0;
3194 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3195 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3196 ha->nvram_npiv_size, ha->max_fibre_devices);
3200 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3201 ha->nvram_conf_off, ha->nvram_data_off);
3204 ret = ha->isp_ops->iospace_config(ha);
3210 pdev->device, pdev->irq, ha->iobase);
3211 mutex_init(&ha->vport_lock);
3212 mutex_init(&ha->mq_lock);
3213 init_completion(&ha->mbx_cmd_comp);
3214 complete(&ha->mbx_cmd_comp);
3215 init_completion(&ha->mbx_intr_comp);
3216 init_completion(&ha->dcbx_comp);
3217 init_completion(&ha->lb_portup_comp);
3219 set_bit(0, (unsigned long *) ha->vp_idx_map);
3224 ha->flags.enable_64bit_addressing ? "enable" :
3234 req->max_q_depth = MAX_Q_DEPTH;
3236 req->max_q_depth = ql2xmaxqdepth;
3241 ret = -ENOMEM;
3246 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3248 host = base_vha->host;
3249 base_vha->req = req;
3251 base_vha->mgmt_svr_loop_id =
3254 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3255 base_vha->vp_idx;
3258 ha->mr.fcport.vha = base_vha;
3259 ha->mr.fcport.port_type = FCT_UNKNOWN;
3260 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3261 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3262 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3263 ha->mr.fcport.scan_state = 1;
3272 host->sg_tablesize = 32;
3275 host->sg_tablesize = QLA_SG_ALL;
3277 host->max_id = ha->max_fibre_devices;
3278 host->cmd_per_lun = 3;
3279 host->unique_id = host->host_no;
3288 host->max_cmd_len = 32;
3290 host->max_cmd_len = MAX_CMDSZ;
3291 host->max_channel = MAX_BUSES - 1;
3292 /* Older HBAs support only 16-bit LUNs */
3295 host->max_lun = 0xffff;
3297 host->max_lun = ql2xmaxlun;
3298 host->transportt = qla2xxx_transport_template;
3299 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3304 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3305 host->this_id, host->cmd_per_lun, host->unique_id,
3306 host->max_cmd_len, host->max_channel, host->max_lun,
3307 host->transportt, sht->vendor_id);
3309 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3322 ret = -ENODEV;
3326 if (ha->mqenable) {
3327 /* number of hardware queues supported by blk/scsi-mq*/
3328 host->nr_hw_queues = ha->max_qpairs;
3331 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3334 host->nr_hw_queues = ha->max_qpairs;
3336 "FC-NVMe support is enabled, HW queues=%d\n",
3337 host->nr_hw_queues);
3340 "blk/scsi-mq disabled.\n");
3349 rsp->req = req;
3350 req->rsp = rsp;
3353 ha->rsp_q_map[0] = rsp;
3354 ha->req_q_map[0] = req;
3355 set_bit(0, ha->req_qid_map);
3356 set_bit(0, ha->rsp_qid_map);
3359 /* FWI2-capable only. */
3360 req->req_q_in = &ha->iobase->isp24.req_q_in;
3361 req->req_q_out = &ha->iobase->isp24.req_q_out;
3362 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3363 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3364 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3366 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3367 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3368 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3369 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3373 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3374 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3375 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3376 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3380 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3381 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3382 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3386 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3387 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3389 "req->req_q_in=%p req->req_q_out=%p "
3390 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3391 req->req_q_in, req->req_q_out,
3392 rsp->rsp_q_in, rsp->rsp_q_out);
3394 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3395 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3397 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3398 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3401 if (unlikely(!ha->wq)) {
3402 ret = -ENOMEM;
3406 if (ha->isp_ops->initialize_adapter(base_vha)) {
3408 "Failed to initialize adapter - Adapter flags %x.\n",
3409 base_vha->device_flags);
3428 ret = -ENODEV;
3433 host->can_queue = QLAFX00_MAX_CANQUEUE;
3435 host->can_queue = req->num_outstanding_cmds - 10;
3439 host->can_queue, base_vha->req,
3440 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3443 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3444 ha->mqenable = 0;
3446 if (ha->mqenable) {
3456 for (i = 0; i < ha->max_qpairs; i++)
3461 if (ha->flags.running_gold_fw)
3467 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3468 "%s_dpc", base_vha->host_str);
3469 if (IS_ERR(ha->dpc_thread)) {
3472 ret = PTR_ERR(ha->dpc_thread);
3473 ha->dpc_thread = NULL;
3487 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3490 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3491 ha->dpc_lp_wq =
3493 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3495 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3496 ha->dpc_hp_wq =
3498 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3499 INIT_WORK(&ha->idc_state_handler,
3501 INIT_WORK(&ha->nic_core_unrecoverable,
3506 list_add_tail(&base_vha->list, &ha->vp_list);
3507 base_vha->host->irq = ha->pdev->irq;
3519 if (ha->fw_attributes & BIT_4) {
3522 base_vha->flags.difdix_supported = 1;
3547 base_vha->flags.difdix_supported = 0;
3550 ha->isp_ops->enable_intrs(ha);
3554 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3555 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3559 if (IS_T10_PI_CAPABLE(base_vha->hw))
3560 host->dma_alignment = 0x7;
3562 ret = scsi_add_host(host, &pdev->dev);
3566 base_vha->flags.init_done = 1;
3567 base_vha->flags.online = 1;
3568 ha->prev_minidump_failed = 0;
3578 "skipping scsi_scan_host() for non-initiator port\n");
3584 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3588 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3596 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3599 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3601 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3602 base_vha->host_no,
3603 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3607 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3609 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3610 return -ENODEV;
3617 vfree(base_vha->scan.l);
3618 if (base_vha->gnl.l) {
3619 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3620 base_vha->gnl.l, base_vha->gnl.ldma);
3621 base_vha->gnl.l = NULL;
3624 if (base_vha->timer_active)
3626 base_vha->flags.online = 0;
3627 if (ha->dpc_thread) {
3628 struct task_struct *t = ha->dpc_thread;
3630 ha->dpc_thread = NULL;
3635 scsi_host_put(base_vha->host);
3653 if (!ha->nx_pcibase)
3654 iounmap((device_reg_t *)ha->nx_pcibase);
3656 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3658 if (ha->iobase)
3659 iounmap(ha->iobase);
3660 if (ha->cregbase)
3661 iounmap(ha->cregbase);
3663 pci_release_selected_regions(ha->pdev, ha->bars);
3680 ha = base_vha->hw;
3682 spin_lock_irqsave(&ha->vport_slock, flags);
3683 list_for_each_entry(vp, &ha->vp_list, list)
3684 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3690 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3691 spin_unlock_irqrestore(&ha->vport_slock, flags);
3701 ha = vha->hw;
3711 cancel_work_sync(&ha->board_disable);
3713 if (!atomic_read(&pdev->enable_cnt))
3720 /* Turn-off FCE trace */
3721 if (ha->flags.fce_enabled) {
3723 ha->flags.fce_enabled = 0;
3726 /* Turn-off EFT trace */
3727 if (ha->eft)
3732 if (ha->flags.fw_started)
3740 if (vha->timer_active)
3744 vha->flags.online = 0;
3746 /* turn-off interrupts on the card */
3747 if (ha->interrupts_on) {
3748 vha->flags.init_done = 0;
3749 ha->isp_ops->disable_intrs(ha);
3761 /* Deletes all the virtual ports for a given ha */
3768 mutex_lock(&ha->vport_lock);
3769 while (ha->cur_vport_count) {
3770 spin_lock_irqsave(&ha->vport_slock, flags);
3772 BUG_ON(base_vha->list.next == &ha->vp_list);
3773 /* This assumes first entry in ha->vp_list is always base vha */
3774 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3775 scsi_host_get(vha->host);
3777 spin_unlock_irqrestore(&ha->vport_slock, flags);
3778 mutex_unlock(&ha->vport_lock);
3782 fc_vport_terminate(vha->fc_vport);
3783 scsi_host_put(vha->host);
3785 mutex_lock(&ha->vport_lock);
3787 mutex_unlock(&ha->vport_lock);
3795 if (ha->dpc_lp_wq) {
3796 cancel_work_sync(&ha->idc_aen);
3797 destroy_workqueue(ha->dpc_lp_wq);
3798 ha->dpc_lp_wq = NULL;
3801 if (ha->dpc_hp_wq) {
3802 cancel_work_sync(&ha->nic_core_reset);
3803 cancel_work_sync(&ha->idc_state_handler);
3804 cancel_work_sync(&ha->nic_core_unrecoverable);
3805 destroy_workqueue(ha->dpc_hp_wq);
3806 ha->dpc_hp_wq = NULL;
3810 if (ha->dpc_thread) {
3811 struct task_struct *t = ha->dpc_thread;
3814 * qla2xxx_wake_dpc checks for ->dpc_thread
3817 ha->dpc_thread = NULL;
3827 iounmap((device_reg_t *)ha->nx_pcibase);
3829 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3831 if (ha->iobase)
3832 iounmap(ha->iobase);
3834 if (ha->cregbase)
3835 iounmap(ha->cregbase);
3837 if (ha->mqiobase)
3838 iounmap(ha->mqiobase);
3840 if (ha->msixbase)
3841 iounmap(ha->msixbase);
3866 ha = base_vha->hw;
3870 cancel_work_sync(&ha->board_disable);
3873 * If the PCI device is disabled then there was a PCI-disconnect and
3877 if (!atomic_read(&pdev->enable_cnt)) {
3878 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3879 base_vha->gnl.l, base_vha->gnl.ldma);
3880 base_vha->gnl.l = NULL;
3881 scsi_host_put(base_vha->host);
3892 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3897 if (ha->flags.fw_started)
3905 "Error while clearing DRV-Presence.\n");
3915 dma_free_coherent(&ha->pdev->dev,
3916 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3918 base_vha->gnl.l = NULL;
3922 vfree(base_vha->scan.l);
3934 if (base_vha->timer_active)
3937 base_vha->flags.online = 0;
3940 if (ha->exlogin_buf)
3944 if (ha->exchoffld_buf)
3953 fc_remove_host(base_vha->host);
3955 scsi_remove_host(base_vha->host);
3961 scsi_host_put(base_vha->host);
3965 pci_release_selected_regions(ha->pdev, ha->bars);
3977 spin_lock_irqsave(&list->lock, flags);
3978 list_for_each_entry_safe(item, next, &list->head, list) {
3979 list_del(&item->list);
3980 if (item == &item->vha->default_item)
3984 spin_unlock_irqrestore(&list->lock, flags);
3990 struct qla_hw_data *ha = vha->hw;
3995 if (vha->timer_active)
3999 vha->flags.online = 0;
4001 /* turn-off interrupts on the card */
4002 if (ha->interrupts_on) {
4003 vha->flags.init_done = 0;
4004 ha->isp_ops->disable_intrs(ha);
4012 if (ha->wq) {
4013 destroy_workqueue(ha->wq);
4014 ha->wq = NULL;
4018 qla24xx_free_purex_list(&vha->purex_list);
4034 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4043 if (!fcport->rport)
4046 if (fcport->rport) {
4047 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4049 __func__, fcport->port_name, fcport->rport,
4050 fcport->rport->roles);
4051 fc_remote_port_delete(fcport->rport);
4068 if (IS_QLAFX00(vha->hw)) {
4074 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4075 vha->vp_idx == fcport->vha->vp_idx) {
4084 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4090 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4101 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4103 fcport->loop_id != FC_NO_LOOP_ID &&
4104 (fcport->flags & FCF_FCP2_DEVICE) &&
4105 fcport->port_type == FCT_TARGET &&
4109 fcport->flags, fcport->port_type,
4110 fcport->d_id.b24, fcport->port_name);
4113 fcport->scan_state = 0;
4126 set_bit(i, ha->loop_id_map);
4127 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4128 set_bit(BROADCAST, ha->loop_id_map);
4147 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4148 if (!ha->vp_map)
4152 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4153 &ha->init_cb_dma, GFP_KERNEL);
4154 if (!ha->init_cb)
4157 rc = btree_init32(&ha->host_map);
4164 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4165 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4166 if (!ha->gid_list)
4169 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4170 if (!ha->srb_mempool)
4182 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4184 if (!ha->ctx_mempool)
4186 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4188 ctx_cachep, ha->ctx_mempool);
4192 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4193 if (!ha->nvram)
4197 ha->pdev->device);
4198 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4200 if (!ha->s_dma_pool)
4203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4205 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4208 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4210 if (!ha->dl_dma_pool) {
4211 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4216 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4218 if (!ha->fcp_cmnd_dma_pool) {
4219 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4229 ha->dif_bundl_pool = dma_pool_create(name,
4230 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4231 if (!ha->dif_bundl_pool) {
4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4238 INIT_LIST_HEAD(&ha->pool.good.head);
4239 INIT_LIST_HEAD(&ha->pool.unusable.head);
4240 ha->pool.good.count = 0;
4241 ha->pool.unusable.count = 0;
4245 ql_dbg_pci(ql_dbg_init, ha->pdev,
4248 return -ENOMEM;
4250 ha->dif_bundle_kallocs++;
4252 dsd->dsd_addr = dma_pool_alloc(
4253 ha->dif_bundl_pool, GFP_ATOMIC,
4254 &dsd->dsd_list_dma);
4255 if (!dsd->dsd_addr) {
4256 ql_dbg_pci(ql_dbg_init, ha->pdev,
4258 "%s: failed alloc ->dsd_addr\n",
4261 ha->dif_bundle_kallocs--;
4264 ha->dif_bundle_dma_allocs++;
4270 if (MSD(dsd->dsd_list_dma) ^
4271 MSD(dsd->dsd_list_dma + bufsize)) {
4272 list_add_tail(&dsd->list,
4273 &ha->pool.unusable.head);
4274 ha->pool.unusable.count++;
4276 list_add_tail(&dsd->list,
4277 &ha->pool.good.head);
4278 ha->pool.good.count++;
4284 &ha->pool.good.head, list) {
4285 list_del(&dsd->list);
4286 dma_pool_free(ha->dif_bundl_pool,
4287 dsd->dsd_addr, dsd->dsd_list_dma);
4288 ha->dif_bundle_dma_allocs--;
4290 ha->dif_bundle_kallocs--;
4293 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4295 __func__, ha->pool.good.count,
4296 ha->pool.unusable.count);
4299 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4301 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4302 ha->dif_bundl_pool);
4308 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4309 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4310 if (!ha->sns_cmd)
4312 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4313 "sns_cmd: %p.\n", ha->sns_cmd);
4316 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4317 &ha->ms_iocb_dma);
4318 if (!ha->ms_iocb)
4321 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4322 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4323 if (!ha->ct_sns)
4325 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4327 ha->ms_iocb, ha->ct_sns);
4333 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4337 (*req)->length = req_len;
4338 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4339 ((*req)->length + 1) * sizeof(request_t),
4340 &(*req)->dma, GFP_KERNEL);
4341 if (!(*req)->ring) {
4342 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4349 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4353 (*rsp)->hw = ha;
4354 (*rsp)->length = rsp_len;
4355 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4356 ((*rsp)->length + 1) * sizeof(response_t),
4357 &(*rsp)->dma, GFP_KERNEL);
4358 if (!(*rsp)->ring) {
4359 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4363 (*req)->rsp = *rsp;
4364 (*rsp)->req = *req;
4365 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4366 "req=%p req->length=%d req->ring=%p rsp=%p "
4367 "rsp->length=%d rsp->ring=%p.\n",
4368 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4369 (*rsp)->ring);
4371 if (ha->nvram_npiv_size) {
4372 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4375 if (!ha->npiv_info) {
4376 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4381 ha->npiv_info = NULL;
4383 /* Get consistent memory allocated for EX-INIT-CB. */
4386 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4387 &ha->ex_init_cb_dma);
4388 if (!ha->ex_init_cb)
4390 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4391 "ex_init_cb=%p.\n", ha->ex_init_cb);
4394 /* Get consistent memory allocated for Special Features-CB. */
4396 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4397 &ha->sf_init_cb_dma);
4398 if (!ha->sf_init_cb)
4400 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4401 "sf_init_cb=%p.\n", ha->sf_init_cb);
4405 /* Get consistent memory allocated for Async Port-Database. */
4407 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4408 &ha->async_pd_dma);
4409 if (!ha->async_pd)
4411 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4412 "async_pd=%p.\n", ha->async_pd);
4415 INIT_LIST_HEAD(&ha->vp_list);
4418 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4421 if (!ha->loop_id_map)
4425 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4426 "loop_id_map=%p.\n", ha->loop_id_map);
4429 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4430 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4431 if (!ha->sfp_data) {
4432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4433 "Unable to allocate memory for SFP read-data.\n");
4437 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4438 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4440 if (!ha->flt) {
4441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4447 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4450 if (!ha->purex_dma_pool) {
4451 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4456 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4457 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4458 ha->elsrej.size,
4459 &ha->elsrej.cdma,
4461 if (!ha->elsrej.c) {
4462 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4466 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4467 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4468 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4470 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4471 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4472 &ha->lsrjt.cdma, GFP_KERNEL);
4473 if (!ha->lsrjt.c) {
4474 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4482 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4483 ha->elsrej.c, ha->elsrej.cdma);
4485 dma_pool_destroy(ha->purex_dma_pool);
4487 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4488 ha->flt, ha->flt_dma);
4491 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4492 ha->sfp_data, ha->sfp_data_dma);
4494 kfree(ha->loop_id_map);
4496 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4498 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4500 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4502 kfree(ha->npiv_info);
4504 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4505 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4506 (*rsp)->ring = NULL;
4507 (*rsp)->dma = 0;
4512 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4513 sizeof(request_t), (*req)->ring, (*req)->dma);
4514 (*req)->ring = NULL;
4515 (*req)->dma = 0;
4520 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4521 ha->ct_sns, ha->ct_sns_dma);
4522 ha->ct_sns = NULL;
4523 ha->ct_sns_dma = 0;
4525 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4526 ha->ms_iocb = NULL;
4527 ha->ms_iocb_dma = 0;
4529 if (ha->sns_cmd)
4530 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4531 ha->sns_cmd, ha->sns_cmd_dma);
4536 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4538 list_del(&dsd->list);
4539 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4540 dsd->dsd_list_dma);
4541 ha->dif_bundle_dma_allocs--;
4543 ha->dif_bundle_kallocs--;
4544 ha->pool.unusable.count--;
4546 dma_pool_destroy(ha->dif_bundl_pool);
4547 ha->dif_bundl_pool = NULL;
4552 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4553 ha->fcp_cmnd_dma_pool = NULL;
4557 dma_pool_destroy(ha->dl_dma_pool);
4558 ha->dl_dma_pool = NULL;
4561 dma_pool_destroy(ha->s_dma_pool);
4562 ha->s_dma_pool = NULL;
4564 kfree(ha->nvram);
4565 ha->nvram = NULL;
4567 mempool_destroy(ha->ctx_mempool);
4568 ha->ctx_mempool = NULL;
4570 mempool_destroy(ha->srb_mempool);
4571 ha->srb_mempool = NULL;
4573 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4574 ha->gid_list,
4575 ha->gid_list_dma);
4576 ha->gid_list = NULL;
4577 ha->gid_list_dma = 0;
4581 btree_destroy32(&ha->host_map);
4583 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4584 ha->init_cb_dma);
4585 ha->init_cb = NULL;
4586 ha->init_cb_dma = 0;
4588 kfree(ha->vp_map);
4589 ha->vp_map = NULL;
4593 return -ENOMEM;
4602 struct qla_hw_data *ha = vha->hw;
4615 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4623 if (temp != ha->exlogin_size) {
4625 ha->exlogin_size = temp;
4632 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4635 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4636 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4637 if (!ha->exlogin_buf) {
4638 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4640 return -ENOMEM;
4645 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4664 if (ha->exlogin_buf) {
4665 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4666 ha->exlogin_buf, ha->exlogin_buf_dma);
4667 ha->exlogin_buf = NULL;
4668 ha->exlogin_size = 0;
4676 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4679 if (max_cnt > vha->hw->max_exchg)
4680 max_cnt = vha->hw->max_exchg;
4683 if (vha->ql2xiniexchg > max_cnt)
4684 vha->ql2xiniexchg = max_cnt;
4686 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4687 *ret_cnt = vha->ql2xiniexchg;
4690 if (vha->ql2xexchoffld > max_cnt) {
4691 vha->ql2xexchoffld = max_cnt;
4692 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4695 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4696 *ret_cnt = vha->ql2xexchoffld;
4698 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4700 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4701 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4703 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4717 struct qla_hw_data *ha = vha->hw;
4719 if (!ha->flags.exchoffld_enabled)
4728 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4739 if (totsz != ha->exchoffld_size) {
4742 ha->exchoffld_size = 0;
4743 ha->flags.exchoffld_enabled = 0;
4747 ha->exchoffld_size = totsz;
4755 ha->exchoffld_size);
4758 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4759 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4760 if (!ha->exchoffld_buf) {
4761 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4764 if (ha->max_exchg >
4766 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4767 } else if (ha->max_exchg >
4769 ha->max_exchg -= 512;
4771 ha->flags.exchoffld_enabled = 0;
4772 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4775 ha->exchoffld_size = 0;
4777 return -ENOMEM;
4779 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4782 ha->exchoffld_size = 0;
4783 ha->flags.exchoffld_enabled = 0;
4786 ha->exchoffld_size, actual_cnt, size, totsz);
4797 /* re-adjust number of target exchange */
4798 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4801 icb->exchange_count = 0;
4803 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4818 if (ha->exchoffld_buf) {
4819 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4820 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4821 ha->exchoffld_buf = NULL;
4822 ha->exchoffld_size = 0;
4836 struct fwdt *fwdt = ha->fwdt;
4839 if (ha->fce)
4840 dma_free_coherent(&ha->pdev->dev,
4841 FCE_SIZE, ha->fce, ha->fce_dma);
4843 if (ha->eft)
4844 dma_free_coherent(&ha->pdev->dev,
4845 EFT_SIZE, ha->eft, ha->eft_dma);
4847 vfree(ha->fw_dump);
4849 ha->fce = NULL;
4850 ha->fce_dma = 0;
4851 ha->flags.fce_enabled = 0;
4852 ha->eft = NULL;
4853 ha->eft_dma = 0;
4854 ha->fw_dumped = false;
4855 ha->fw_dump_cap_flags = 0;
4856 ha->fw_dump_reading = 0;
4857 ha->fw_dump = NULL;
4858 ha->fw_dump_len = 0;
4861 vfree(fwdt->template);
4862 fwdt->template = NULL;
4863 fwdt->length = 0;
4879 if (ha->mctp_dump)
4880 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4881 ha->mctp_dump_dma);
4882 ha->mctp_dump = NULL;
4884 mempool_destroy(ha->srb_mempool);
4885 ha->srb_mempool = NULL;
4887 if (ha->dcbx_tlv)
4888 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4889 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4890 ha->dcbx_tlv = NULL;
4892 if (ha->xgmac_data)
4893 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4894 ha->xgmac_data, ha->xgmac_data_dma);
4895 ha->xgmac_data = NULL;
4897 if (ha->sns_cmd)
4898 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4899 ha->sns_cmd, ha->sns_cmd_dma);
4900 ha->sns_cmd = NULL;
4901 ha->sns_cmd_dma = 0;
4903 if (ha->ct_sns)
4904 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4905 ha->ct_sns, ha->ct_sns_dma);
4906 ha->ct_sns = NULL;
4907 ha->ct_sns_dma = 0;
4909 if (ha->sfp_data)
4910 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4911 ha->sfp_data_dma);
4912 ha->sfp_data = NULL;
4914 if (ha->flt)
4915 dma_free_coherent(&ha->pdev->dev,
4917 ha->flt, ha->flt_dma);
4918 ha->flt = NULL;
4919 ha->flt_dma = 0;
4921 if (ha->ms_iocb)
4922 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4923 ha->ms_iocb = NULL;
4924 ha->ms_iocb_dma = 0;
4926 if (ha->sf_init_cb)
4927 dma_pool_free(ha->s_dma_pool,
4928 ha->sf_init_cb, ha->sf_init_cb_dma);
4930 if (ha->ex_init_cb)
4931 dma_pool_free(ha->s_dma_pool,
4932 ha->ex_init_cb, ha->ex_init_cb_dma);
4933 ha->ex_init_cb = NULL;
4934 ha->ex_init_cb_dma = 0;
4936 if (ha->async_pd)
4937 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4938 ha->async_pd = NULL;
4939 ha->async_pd_dma = 0;
4941 dma_pool_destroy(ha->s_dma_pool);
4942 ha->s_dma_pool = NULL;
4944 if (ha->gid_list)
4945 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4946 ha->gid_list, ha->gid_list_dma);
4947 ha->gid_list = NULL;
4948 ha->gid_list_dma = 0;
4950 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4955 &ha->base_qpair->dsd_list, list) {
4956 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4957 dsd_ptr->dsd_list_dma);
4958 list_del(&dsd_ptr->list);
4963 dma_pool_destroy(ha->dl_dma_pool);
4964 ha->dl_dma_pool = NULL;
4966 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4967 ha->fcp_cmnd_dma_pool = NULL;
4969 mempool_destroy(ha->ctx_mempool);
4970 ha->ctx_mempool = NULL;
4972 if (ql2xenabledif && ha->dif_bundl_pool) {
4975 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4977 list_del(&dsd->list);
4978 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4979 dsd->dsd_list_dma);
4980 ha->dif_bundle_dma_allocs--;
4982 ha->dif_bundle_kallocs--;
4983 ha->pool.unusable.count--;
4985 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4986 list_del(&dsd->list);
4987 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4988 dsd->dsd_list_dma);
4989 ha->dif_bundle_dma_allocs--;
4991 ha->dif_bundle_kallocs--;
4995 dma_pool_destroy(ha->dif_bundl_pool);
4996 ha->dif_bundl_pool = NULL;
5001 if (ha->init_cb)
5002 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5003 ha->init_cb, ha->init_cb_dma);
5005 dma_pool_destroy(ha->purex_dma_pool);
5006 ha->purex_dma_pool = NULL;
5008 if (ha->elsrej.c) {
5009 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5010 ha->elsrej.c, ha->elsrej.cdma);
5011 ha->elsrej.c = NULL;
5014 if (ha->lsrjt.c) {
5015 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5016 ha->lsrjt.cdma);
5017 ha->lsrjt.c = NULL;
5020 ha->init_cb = NULL;
5021 ha->init_cb_dma = 0;
5023 vfree(ha->optrom_buffer);
5024 ha->optrom_buffer = NULL;
5025 kfree(ha->nvram);
5026 ha->nvram = NULL;
5027 kfree(ha->npiv_info);
5028 ha->npiv_info = NULL;
5029 kfree(ha->swl);
5030 ha->swl = NULL;
5031 kfree(ha->loop_id_map);
5032 ha->sf_init_cb = NULL;
5033 ha->sf_init_cb_dma = 0;
5034 ha->loop_id_map = NULL;
5036 kfree(ha->vp_map);
5037 ha->vp_map = NULL;
5048 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5057 vha->host = host;
5058 vha->host_no = host->host_no;
5059 vha->hw = ha;
5061 vha->qlini_mode = ql2x_ini_mode;
5062 vha->ql2xexchoffld = ql2xexchoffld;
5063 vha->ql2xiniexchg = ql2xiniexchg;
5065 INIT_LIST_HEAD(&vha->vp_fcports);
5066 INIT_LIST_HEAD(&vha->work_list);
5067 INIT_LIST_HEAD(&vha->list);
5068 INIT_LIST_HEAD(&vha->qla_cmd_list);
5069 INIT_LIST_HEAD(&vha->logo_list);
5070 INIT_LIST_HEAD(&vha->plogi_ack_list);
5071 INIT_LIST_HEAD(&vha->qp_list);
5072 INIT_LIST_HEAD(&vha->gnl.fcports);
5073 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5075 INIT_LIST_HEAD(&vha->purex_list.head);
5076 spin_lock_init(&vha->purex_list.lock);
5078 spin_lock_init(&vha->work_lock);
5079 spin_lock_init(&vha->cmd_list_lock);
5080 init_waitqueue_head(&vha->fcport_waitQ);
5081 init_waitqueue_head(&vha->vref_waitq);
5086 vha->gnl.size = sizeof(struct get_name_list_extended) *
5087 (ha->max_loop_id + 1);
5088 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5089 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5090 if (!vha->gnl.l) {
5093 scsi_host_put(vha->host);
5098 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5099 vha->scan.l = vmalloc(vha->scan.size);
5100 if (!vha->scan.l) {
5103 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5104 vha->gnl.l, vha->gnl.ldma);
5105 vha->gnl.l = NULL;
5106 scsi_host_put(vha->host);
5109 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5111 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5112 QLA2XXX_DRIVER_NAME, vha->host_no);
5115 vha->host, vha->hw, vha,
5116 dev_name(&(ha->pdev->dev)));
5126 if (test_bit(UNLOADING, &vha->dpc_flags))
5138 INIT_LIST_HEAD(&e->list);
5139 e->type = type;
5140 e->flags = QLA_EVT_FLAG_FREE;
5150 spin_lock_irqsave(&vha->work_lock, flags);
5151 list_add_tail(&e->list, &vha->work_list);
5153 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5156 spin_unlock_irqrestore(&vha->work_lock, flags);
5159 queue_work(vha->hw->wq, &vha->iocb_work);
5174 e->u.aen.code = code;
5175 e->u.aen.data = data;
5188 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5203 e->u.logio.fcport = fcport; \
5205 e->u.logio.data[0] = data[0]; \
5206 e->u.logio.data[1] = data[1]; \
5208 fcport->flags |= FCF_ASYNC_ACTIVE; \
5227 e->u.uevent.code = code;
5240 vha->host_no);
5246 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5259 e->u.aenfx.evtcode = evtcode;
5260 e->u.aenfx.count = cnt;
5261 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5269 if (IS_SW_RESV_ADDR(fcport->d_id))
5272 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5273 if (fcport->disc_state == DSC_UPD_FCPORT) {
5274 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5277 fcport->jiffies_at_registration = jiffies;
5278 fcport->sec_since_registration = 0;
5279 fcport->next_disc_state = DSC_DELETED;
5281 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5283 queue_work(system_unbound_wq, &fcport->reg_work);
5292 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5297 __func__, __LINE__, e->u.new_sess.port_name);
5299 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5300 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5302 fcport->d_id = e->u.new_sess.id;
5304 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5305 memcpy(fcport->node_name,
5306 pla->iocb.u.isp24.u.plogi.node_name,
5312 pla->ref_count--;
5315 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5318 fcport->d_id = e->u.new_sess.id;
5319 fcport->flags |= FCF_FABRIC_DEVICE;
5320 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5321 fcport->tgt_short_link_down_cnt = 0;
5323 memcpy(fcport->port_name, e->u.new_sess.port_name,
5326 fcport->fc4_type = e->u.new_sess.fc4_type;
5327 if (NVME_PRIORITY(vha->hw, fcport))
5328 fcport->do_prli_nvme = 1;
5330 fcport->do_prli_nvme = 0;
5332 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5333 fcport->dm_login_expire = jiffies +
5335 fcport->fc4_type = FS_FC4TYPE_FCP;
5336 fcport->n2n_flag = 1;
5337 if (vha->flags.nvme_enabled)
5338 fcport->fc4_type |= FS_FC4TYPE_NVME;
5344 __func__, e->u.new_sess.port_name);
5347 list_del(&pla->list);
5353 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5356 e->u.new_sess.port_name, 1);
5361 __func__, tfcp->port_name, tfcp->disc_state,
5362 tfcp->fw_login_state);
5366 list_add_tail(&fcport->list, &vha->vp_fcports);
5372 pla->ref_count--;
5375 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5378 fcport->id_changed = 1;
5379 fcport->scan_state = QLA_FCPORT_FOUND;
5380 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5381 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5384 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5387 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5388 fcport->local = 0;
5389 fcport->loop_id =
5391 pla->iocb.u.isp24.nport_handle);
5392 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5395 pla->iocb.u.isp24.u.prli.wd3_lo);
5398 fcport->conf_compl_supported = 1;
5401 fcport->port_type = FCT_INITIATOR;
5403 fcport->port_type = FCT_TARGET;
5409 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5411 &e->u.new_sess.id, 1);
5418 __func__, tfcp->port_name, tfcp->disc_state,
5419 tfcp->fw_login_state);
5421 switch (tfcp->disc_state) {
5425 fcport->login_pause = 1;
5426 tfcp->conflict = fcport;
5429 fcport->login_pause = 1;
5430 tfcp->conflict = fcport;
5435 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5439 if (N2N_TOPO(vha->hw)) {
5440 fcport->flags &= ~FCF_FABRIC_DEVICE;
5441 fcport->keep_nport_handle = 1;
5442 if (vha->flags.nvme_enabled) {
5443 fcport->fc4_type =
5445 fcport->n2n_flag = 1;
5447 fcport->fw_login_state = 0;
5449 schedule_delayed_work(&vha->scan.scan_work, 5);
5459 list_del(&pla->list);
5467 struct srb *sp = e->u.iosb.sp;
5470 rval = qla2x00_start_sp(sp);
5473 "%s: %s: Re-issue IOCB failed (%d).\n",
5474 __func__, sp->name, rval);
5475 qla24xx_sp_unmap(vha, sp);
5487 spin_lock_irqsave(&vha->work_lock, flags);
5488 list_splice_init(&vha->work_list, &work);
5489 spin_unlock_irqrestore(&vha->work_lock, flags);
5493 switch (e->type) {
5495 fc_host_post_event(vha->host, fc_get_event_number(),
5496 e->u.aen.code, e->u.aen.data);
5499 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5502 qla2x00_async_login(vha, e->u.logio.fcport,
5503 e->u.logio.data);
5506 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5509 qla2x00_async_adisc(vha, e->u.logio.fcport,
5510 e->u.logio.data);
5513 qla2x00_uevent_emit(vha, e->u.uevent.code);
5519 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5528 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5529 e->u.fcport.opt);
5532 qla24xx_async_prli(vha, e->u.fcport.fcport);
5535 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5538 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5544 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5547 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5548 e->u.logio.data);
5551 qla_fab_async_scan(vha, e->u.iosb.sp);
5554 qla_fab_scan_finish(vha, e->u.iosb.sp);
5557 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5563 qla_do_iidma_work(vha, e->u.fcport.fcport);
5567 e->u.fcport.fcport);
5575 /* put 'work' at head of 'vha->work_list' */
5576 spin_lock_irqsave(&vha->work_lock, flags);
5577 list_splice(&work, &vha->work_list);
5578 spin_unlock_irqrestore(&vha->work_lock, flags);
5581 list_del_init(&e->list);
5582 if (e->flags & QLA_EVT_FLAG_FREE)
5597 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5613 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5618 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5619 fcport->login_retry) {
5620 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5621 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5622 fcport->disc_state == DSC_LOGIN_COMPLETE)
5625 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5626 fcport->disc_state == DSC_DELETE_PEND) {
5629 if (vha->hw->current_topology != ISP_CFG_NL) {
5633 } else if (vha->hw->current_topology ==
5635 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5638 } else if (vha->hw->current_topology ==
5640 fcport->login_retry--;
5645 fcport->old_loop_id =
5646 fcport->loop_id;
5649 fcport->loop_id);
5654 &vha->dpc_flags);
5658 fcport->login_retry,
5659 fcport->loop_id);
5661 fcport->login_retry = 0;
5664 if (fcport->login_retry == 0 &&
5670 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5675 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5681 /* Schedule work on any of the dpc-workqueues */
5685 struct qla_hw_data *ha = base_vha->hw;
5689 if (ha->dpc_lp_wq)
5690 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5694 if (!ha->flags.nic_core_reset_hdlr_active) {
5695 if (ha->dpc_hp_wq)
5696 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5703 if (ha->dpc_hp_wq)
5704 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5707 if (ha->dpc_hp_wq)
5708 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5712 "Unknown work-code=0x%x.\n", work_code);
5724 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5730 if (ha->flags.nic_core_reset_owner) {
5731 ha->flags.nic_core_reset_owner = 0;
5746 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5792 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5802 if (!ha->flags.nic_core_reset_hdlr_active) {
5815 ha->flags.nic_core_reset_hdlr_active = 1;
5821 ha->flags.nic_core_reset_hdlr_active = 0;
5831 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5867 struct qla_hw_data *ha = base_vha->hw;
5879 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5892 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5905 /* Clear lock-id by setting 0xff */
5910 /* Clear lock-recovery by setting 0x0 */
5965 struct qla_hw_data *ha = base_vha->hw;
5969 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5974 /* Setting lock-id to our function-number */
5976 ha->portnum);
5984 /* Retry/Perform IDC-Lock recovery */
6004 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6007 /* Domain Controller is always logged-out. */
6019 le16_to_cpu(purex->nport_handle), pdb)) {
6022 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6023 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6033 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6058 struct qla_hw_data *ha = vha->hw;
6060 (struct purex_entry_24xx *)&item->iocb;
6077 "-------- ELS REQ -------\n");
6089 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6097 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6105 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6108 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6112 rsp_els->entry_type = ELS_IOCB_TYPE;
6113 rsp_els->entry_count = 1;
6114 rsp_els->sys_define = 0;
6115 rsp_els->entry_status = 0;
6116 rsp_els->handle = 0;
6117 rsp_els->nport_handle = purex->nport_handle;
6118 rsp_els->tx_dsd_count = cpu_to_le16(1);
6119 rsp_els->vp_index = purex->vp_idx;
6120 rsp_els->sof_type = EST_SOFI3;
6121 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6122 rsp_els->rx_dsd_count = 0;
6123 rsp_els->opcode = purex->els_frame_payload[0];
6125 rsp_els->d_id[0] = purex->s_id[0];
6126 rsp_els->d_id[1] = purex->s_id[1];
6127 rsp_els->d_id[2] = purex->s_id[2];
6129 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6130 rsp_els->rx_byte_count = 0;
6131 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6133 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6134 rsp_els->tx_len = rsp_els->tx_byte_count;
6136 rsp_els->rx_address = 0;
6137 rsp_els->rx_len = 0;
6140 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6141 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6142 sizeof(rsp_payload->hdr));
6145 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6146 rsp_payload->ls_req_info_desc.desc_len =
6147 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6148 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6149 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6152 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6153 rsp_payload->ls_req_info_desc2.desc_len =
6154 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6155 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6156 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6159 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6160 rsp_payload->sfp_diag_desc.desc_len =
6161 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6168 /* SFP Flags bits 3-0: Port Tx Laser Type */
6186 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6193 rsp_payload->sfp_diag_desc.temperature = trx[0];
6194 rsp_payload->sfp_diag_desc.vcc = trx[1];
6195 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6196 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6197 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6202 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6203 rsp_payload->port_speed_desc.desc_len =
6204 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6205 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6207 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6211 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6212 rsp_payload->ls_err_desc.desc_len =
6213 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6218 rsp_payload->ls_err_desc.link_fail_cnt =
6219 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6220 rsp_payload->ls_err_desc.loss_sync_cnt =
6221 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6222 rsp_payload->ls_err_desc.loss_sig_cnt =
6223 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6224 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6225 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6226 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6227 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6228 rsp_payload->ls_err_desc.inval_crc_cnt =
6229 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6230 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6235 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6236 rsp_payload->port_name_diag_desc.desc_len =
6237 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6238 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6239 vha->node_name,
6240 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6241 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6242 vha->port_name,
6243 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6245 /* F-Port Portname Descriptor */
6246 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6247 rsp_payload->port_name_direct_desc.desc_len =
6248 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6249 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6250 vha->fabric_node_name,
6251 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6252 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6253 vha->fabric_port_name,
6254 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6257 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6258 rsp_payload->buffer_credit_desc.desc_len =
6259 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6260 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6261 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6262 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6264 if (ha->flags.plogi_template_valid) {
6266 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6267 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6274 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6275 rsp_payload->optical_elmt_desc[0].desc_len =
6276 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6278 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6279 rsp_payload->optical_elmt_desc[1].desc_len =
6280 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6282 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6283 rsp_payload->optical_elmt_desc[2].desc_len =
6284 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6286 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6287 rsp_payload->optical_elmt_desc[3].desc_len =
6288 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6290 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6291 rsp_payload->optical_elmt_desc[4].desc_len =
6292 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6301 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6302 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6303 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6304 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6305 rsp_payload->optical_elmt_desc[0].element_flags =
6309 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6310 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6311 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6312 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6313 rsp_payload->optical_elmt_desc[1].element_flags =
6317 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6318 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6319 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6320 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6321 rsp_payload->optical_elmt_desc[2].element_flags =
6325 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6326 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6327 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6328 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6329 rsp_payload->optical_elmt_desc[3].element_flags =
6333 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6334 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6335 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6336 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6337 rsp_payload->optical_elmt_desc[4].element_flags =
6345 rsp_payload->optical_elmt_desc[0].element_flags |=
6353 rsp_payload->optical_elmt_desc[1].element_flags |=
6361 rsp_payload->optical_elmt_desc[2].element_flags |=
6369 rsp_payload->optical_elmt_desc[3].element_flags |=
6377 rsp_payload->optical_elmt_desc[4].element_flags |=
6387 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6388 rsp_payload->optical_prod_desc.desc_len =
6389 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6395 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6397 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6398 memcpy(rsp_payload->optical_prod_desc.part_number,
6400 sizeof(rsp_payload->optical_prod_desc.part_number));
6401 memcpy(rsp_payload->optical_prod_desc.revision,
6403 sizeof(rsp_payload->optical_prod_desc.revision));
6404 memcpy(rsp_payload->optical_prod_desc.serial_number,
6406 sizeof(rsp_payload->optical_prod_desc.serial_number));
6412 memcpy(rsp_payload->optical_prod_desc.date,
6414 sizeof(rsp_payload->optical_prod_desc.date));
6422 "-------- ELS RSP -------\n");
6426 "-------- ELS RSP PAYLOAD -------\n");
6434 "%s: iocb failed to execute -> %x\n", __func__, rval);
6435 } else if (rsp_els->comp_status) {
6437 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6438 __func__, rsp_els->comp_status,
6439 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6446 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6449 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6452 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6455 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6462 if (item == &item->vha->default_item)
6463 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6474 spin_lock_irqsave(&list->lock, flags);
6475 list_splice_init(&list->head, &head);
6476 spin_unlock_irqrestore(&list->lock, flags);
6479 list_del(&item->list);
6480 item->process_item(item->vha, item);
6496 struct qla_hw_data *ha = base_vha->hw;
6500 /* IDC-unlock implementation using driver-unlock/lock-id
6507 if (data == ha->portnum) {
6509 /* Clearing lock-id by setting 0xff */
6514 /* Retry for IDC-unlock */
6522 /* Retry for IDC-unlock */
6526 "Failed to read drv-lockid, retrying=%d\n", retry);
6533 /* XXX: IDC-unlock implementation using access-control mbx */
6538 /* Retry for IDC-unlock */
6555 struct qla_hw_data *ha = vha->hw;
6560 drv_presence |= (1 << ha->portnum);
6584 struct qla_hw_data *ha = vha->hw;
6589 drv_presence &= ~(1 << ha->portnum);
6612 struct qla_hw_data *ha = vha->hw;
6616 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6617 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6645 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6657 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6685 struct qla_hw_data *ha = base_vha->hw;
6690 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6691 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6710 if (ha->flags.nic_core_reset_owner)
6713 ha->flags.nic_core_reset_owner = 0;
6716 ha->portnum);
6719 if (ha->flags.nic_core_reset_owner)
6722 /* Wait for AEN to change device-state */
6729 /* Wait for AEN to change device-state */
6735 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6738 /* Wait for AEN to change device-state */
6745 (ha->fcoe_dev_init_timeout * HZ);
6755 if (ha->flags.quiesce_owner)
6762 (ha->fcoe_dev_init_timeout * HZ);
6765 if (ha->flags.nic_core_reset_owner)
6768 ha->flags.nic_core_reset_owner = 0;
6800 struct pci_dev *pdev = ha->pdev;
6801 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6806 if (!atomic_read(&pdev->enable_cnt)) {
6808 "PCI device disabled, no action req for PCI error=%lx\n",
6809 base_vha->pci_flags);
6817 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6830 if (base_vha->timer_active)
6833 base_vha->flags.online = 0;
6843 fc_remove_host(base_vha->host);
6845 scsi_remove_host(base_vha->host);
6847 base_vha->flags.init_done = 0;
6857 pci_release_selected_regions(ha->pdev, ha->bars);
6872 * is kick-off by the driver's detect code and starts up
6887 base_vha = pci_get_drvdata(ha->pdev);
6901 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6904 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6907 if (ha->flags.eeh_busy) {
6909 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6913 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6917 ha->dpc_active = 1;
6921 base_vha->dpc_flags);
6926 &base_vha->dpc_flags)) {
6940 &base_vha->dpc_flags)) {
6953 &base_vha->dpc_flags)) {
6958 &base_vha->dpc_flags))) {
6960 /* FCoE-ctx reset failed.
6961 * Escalate to chip-reset
6964 &base_vha->dpc_flags);
6967 &base_vha->dpc_flags);
6975 &base_vha->dpc_flags)) {
6981 &base_vha->dpc_flags)) {
6983 &base_vha->dpc_flags);
6992 &base_vha->dpc_flags)) {
6997 &base_vha->dpc_flags))
6999 &base_vha->dpc_flags);
7007 &base_vha->dpc_flags)) {
7011 &base_vha->hw->mr.fcport,
7017 &base_vha->dpc_flags)) {
7019 * - NO-OP -- await next ISP-ABORT. Preferred method
7021 * when a forced chip-reset occurs.
7022 * - Force -- ISP-ABORT scheduled.
7024 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7028 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7029 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7032 switch (base_vha->qlini_mode) {
7037 !ha->flags.fw_started)
7042 !ha->flags.fw_started)
7050 &base_vha->dpc_flags))) {
7051 base_vha->flags.online = 1;
7054 if (ha->isp_ops->abort_isp(base_vha)) {
7057 &base_vha->dpc_flags);
7060 &base_vha->dpc_flags);
7066 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7067 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7069 (&base_vha->purex_list);
7071 &base_vha->dpc_flags);
7078 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7087 &base_vha->dpc_flags);
7088 if (!ha->flags.quiesce_owner) {
7104 &base_vha->dpc_flags);
7112 &base_vha->dpc_flags) &&
7113 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7118 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7124 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7125 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7126 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7128 if (!base_vha->relogin_jif ||
7129 time_after_eq(jiffies, base_vha->relogin_jif)) {
7130 base_vha->relogin_jif = jiffies + HZ;
7131 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7141 &base_vha->dpc_flags)) {
7149 &base_vha->dpc_flags))) {
7154 &base_vha->dpc_flags);
7164 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7165 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7166 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7171 if (!ha->interrupts_on)
7172 ha->isp_ops->enable_intrs(ha);
7175 &base_vha->dpc_flags)) {
7176 if (ha->beacon_blink_led == 1)
7177 ha->isp_ops->beacon_blink(base_vha);
7182 &base_vha->dpc_flags)) {
7183 if (ha->flags.eeh_busy ||
7184 ha->flags.pci_channel_io_perm_failure)
7189 mutex_lock(&ha->mq_lock);
7190 list_for_each_entry(qpair, &base_vha->qp_list,
7192 qpair->online = online;
7193 mutex_unlock(&ha->mq_lock);
7197 &base_vha->dpc_flags)) {
7198 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7200 if (threshold > ha->orig_fw_xcb_count)
7201 threshold = ha->orig_fw_xcb_count;
7217 &base_vha->dpc_flags)) {
7221 ha->dpc_active = 0;
7233 ha->dpc_active = 0;
7241 struct qla_hw_data *ha = vha->hw;
7242 struct task_struct *t = ha->dpc_thread;
7244 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7258 if (vha->flags.online && !vha->flags.reset_active &&
7259 !atomic_read(&vha->loop_down_timer) &&
7260 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7262 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7268 vha->marker_needed = 1;
7269 } while (!atomic_read(&vha->loop_down_timer) &&
7270 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7276 struct qla_hw_data *ha = vha->hw;
7285 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7286 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7287 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7291 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7293 for (i = 0; i < ha->max_qpairs; i++) {
7294 if (ha->queue_pair_map[i]) {
7295 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7296 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7297 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7301 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7311 struct qla_hw_data *ha = vha->hw;
7313 if (vha->vp_idx)
7316 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7325 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7329 ha->last_heartbeat_run_jiffies = jiffies;
7330 queue_work(ha->wq, &ha->heartbeat_work);
7336 struct qla_hw_data *ha = vha->hw;
7338 if (!ha->flags.eeh_busy)
7340 if (ha->pci_error_state)
7348 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7349 !ha->flags.eeh_flush) {
7353 ha->isp_ops->reset_chip(vha);
7354 ha->isp_ops->disable_intrs(ha);
7356 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7357 ha->eeh_jif = jiffies;
7359 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7360 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7361 pci_clear_master(ha->pdev);
7365 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7387 srb_t *sp;
7389 struct qla_hw_data *ha = vha->hw;
7394 if (ha->flags.eeh_busy) {
7399 ha->flags.eeh_busy);
7406 * the read returns -1 then disable the board.
7408 if (!pci_channel_offline(ha->pdev)) {
7409 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7414 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7415 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7423 if (!vha->vp_idx && IS_QLAFX00(ha))
7426 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7427 vha->link_down_time++;
7429 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7430 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7431 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7432 fcport->tgt_link_down_time++;
7434 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7437 if (atomic_read(&vha->loop_down_timer) > 0 &&
7438 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7439 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7440 && vha->flags.online) {
7442 if (atomic_read(&vha->loop_down_timer) ==
7443 vha->loop_down_abort_time) {
7446 "Loop down - aborting the queues before time expires.\n");
7448 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7449 atomic_set(&vha->loop_state, LOOP_DEAD);
7452 * Schedule an ISP abort to return any FCP2-device
7455 /* NPIV - scan physical port only */
7456 if (!vha->vp_idx) {
7457 spin_lock_irqsave(&ha->hardware_lock,
7459 req = ha->req_q_map[0];
7461 index < req->num_outstanding_cmds;
7465 sp = req->outstanding_cmds[index];
7466 if (!sp)
7468 if (sp->cmd_type != TYPE_SRB)
7470 if (sp->type != SRB_SCSI_CMD)
7472 sfcp = sp->fcport;
7473 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7478 &vha->dpc_flags);
7481 &vha->dpc_flags);
7484 spin_unlock_irqrestore(&ha->hardware_lock,
7491 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7492 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7494 "Loop down - aborting ISP.\n");
7498 &vha->dpc_flags);
7501 &vha->dpc_flags);
7505 "Loop down - seconds remaining %d.\n",
7506 atomic_read(&vha->loop_down_timer));
7509 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7512 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7518 if (vha->hw->flags.edif_enabled)
7522 if (!list_empty(&vha->work_list)) {
7526 spin_lock_irqsave(&vha->work_lock, flags);
7527 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7529 spin_unlock_irqrestore(&vha->work_lock, flags);
7531 queue_work(vha->hw->wq, &vha->iocb_work);
7535 * FC-NVME
7538 index = atomic_read(&ha->nvme_active_aen_cnt);
7539 if (!vha->vp_idx &&
7540 (index != ha->nvme_last_rptd_aen) &&
7541 ha->zio_mode == QLA_ZIO_MODE_6 &&
7542 !ha->flags.host_shutting_down) {
7543 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7546 ha->nvme_last_rptd_aen);
7547 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7551 if (!vha->vp_idx &&
7552 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7556 ha->last_zio_threshold);
7557 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7558 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7566 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7567 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7569 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7570 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7571 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7572 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7573 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7574 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7575 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7579 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7580 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7581 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7586 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7587 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7588 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7589 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7590 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7591 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7651 struct qla_hw_data *ha = vha->hw;
7682 if (!blob->name)
7686 if (blob->fw)
7689 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7691 "Failed to load firmware image (%s).\n", blob->name);
7692 blob->fw = NULL;
7707 for (blob = qla_fw_blobs; blob->name; blob++)
7708 release_firmware(blob->fw);
7714 struct qla_hw_data *ha = vha->hw;
7715 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7724 ha->chip_reset++;
7726 ha->base_qpair->chip_reset = ha->chip_reset;
7727 for (i = 0; i < ha->max_qpairs; i++) {
7728 if (ha->queue_pair_map[i])
7729 ha->queue_pair_map[i]->chip_reset =
7730 ha->base_qpair->chip_reset;
7738 mutex_lock(&ha->mq_lock);
7739 ha->base_qpair->online = 0;
7740 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7741 qpair->online = 0;
7743 mutex_unlock(&ha->mq_lock);
7747 spin_lock_irqsave(&ha->vport_slock, flags);
7748 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7749 atomic_inc(&vp->vref_count);
7750 spin_unlock_irqrestore(&ha->vport_slock, flags);
7752 spin_lock_irqsave(&ha->vport_slock, flags);
7753 atomic_dec(&vp->vref_count);
7755 spin_unlock_irqrestore(&ha->vport_slock, flags);
7758 list_for_each_entry(fcport, &vha->vp_fcports, list)
7759 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7761 spin_lock_irqsave(&ha->vport_slock, flags);
7762 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7763 atomic_inc(&vp->vref_count);
7764 spin_unlock_irqrestore(&ha->vport_slock, flags);
7765 list_for_each_entry(fcport, &vp->vp_fcports, list)
7766 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7767 spin_lock_irqsave(&ha->vport_slock, flags);
7768 atomic_dec(&vp->vref_count);
7770 spin_unlock_irqrestore(&ha->vport_slock, flags);
7778 struct qla_hw_data *ha = vha->hw;
7783 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7785 if (!atomic_read(&pdev->enable_cnt)) {
7787 "PCI device is disabled,state %x\n", state);
7796 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7806 ha->flags.pci_channel_io_perm_failure = 1;
7809 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7827 struct qla_hw_data *ha = base_vha->hw;
7828 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7829 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7834 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7845 spin_lock_irqsave(&ha->hardware_lock, flags);
7847 stat = rd_reg_word(®->hccr);
7851 stat = rd_reg_dword(®->u.isp2300.host_status);
7855 stat = rd_reg_dword(®24->host_status);
7859 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7863 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7878 struct qla_hw_data *ha = base_vha->hw;
7885 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7890 pdev->error_state = pci_channel_io_normal;
7899 if (ha->mem_only)
7906 "Can't re-enable PCI device after reset.\n");
7911 if (ha->isp_ops->pci_config(base_vha))
7914 mutex_lock(&ha->mq_lock);
7915 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7916 qpair->online = 1;
7917 mutex_unlock(&ha->mq_lock);
7919 ha->flags.eeh_busy = 0;
7920 base_vha->flags.online = 1;
7921 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7922 ha->isp_ops->abort_isp(base_vha);
7923 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7926 ha->flags.eeh_busy = 1;
7945 struct qla_hw_data *ha = base_vha->hw;
7957 ha->pci_error_state = QLA_PCI_RESUME;
7964 struct qla_hw_data *ha = vha->hw;
7965 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7969 if (ha->flags.eeh_busy)
7972 spin_lock_irqsave(&base_vha->work_lock, flags);
7973 if (!ha->flags.eeh_busy) {
7974 ha->eeh_jif = jiffies;
7975 ha->flags.eeh_flush = 0;
7977 ha->flags.eeh_busy = 1;
7980 spin_unlock_irqrestore(&base_vha->work_lock, flags);
7992 struct qla_hw_data *ha = vha->hw;
7993 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7995 if (ha->flags.eeh_busy)
7998 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8006 struct qla_hw_data *ha = base_vha->hw;
8018 ha->flags.eeh_busy = 1;
8019 mutex_lock(&ha->mq_lock);
8020 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8021 qpair->online = 0;
8022 mutex_unlock(&ha->mq_lock);
8024 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8033 struct qla_hw_data *ha = base_vha->hw;
8042 ha->flags.eeh_busy = 0;
8043 mutex_lock(&ha->mq_lock);
8044 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8045 qpair->online = 1;
8046 mutex_unlock(&ha->mq_lock);
8048 base_vha->flags.online = 1;
8049 ha->isp_ops->abort_isp(base_vha);
8050 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8055 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8056 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8058 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8061 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8062 vha->irq_offset);
8086 .this_id = -1,
8154 * qla2x00_module_init - Module initialization.
8254 return -ENOMEM;
8263 * If initiator mode is explictly disabled by qlt_init(),
8274 strcat(qla2x00_version_str, "-debug");
8283 ret = -ENODEV;
8298 ret = -ENODEV;
8332 * qla2x00_module_exit - Module cleanup.