Lines Matching refs:tmplt_hdr

2210 	struct qla8044_minidump_template_hdr *tmplt_hdr;
2215 	tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2270 				addr = tmplt_hdr->saved_state_array[index];
2277 			tmplt_hdr->saved_state_array[index] = read_value;
2283 				addr = tmplt_hdr->saved_state_array[index];
2291 				    tmplt_hdr->saved_state_array[index];
2301 			read_value = tmplt_hdr->saved_state_array[index];
2308 			tmplt_hdr->saved_state_array[index] = read_value;
2816 	struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2818 	tmplt_hdr = ha->md_tmplt_hdr;
2820 	    tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2846 	struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2848 	tmplt_hdr = ha->md_tmplt_hdr;
2850 	    tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
3218 	struct qla8044_minidump_template_hdr *tmplt_hdr;
3268 	tmplt_hdr = (struct qla8044_minidump_template_hdr *)
3271 	num_entry_hdr = tmplt_hdr->num_of_entries;
3274 	    "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
3276 	f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
3285 	tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
3299 	tmplt_hdr->driver_timestamp = timestamp;
3302 		(((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
3303 	tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
3304 	    tmplt_hdr->ocm_window_reg[ha->portnum];