Lines Matching refs:irq_value
1322 u32 irq_value, context, port_id, link_rate;
1327 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1328 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1329 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1330 irq_value);
1384 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1402 u32 irq_value;
1405 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1407 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1408 dev_err(dev, "bcast: irq_value = %x not set enable bit\n",
1409 irq_value);
1429 u32 irq_value, irq_mask_old;
1437 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1439 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1447 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1451 if (irq_value & CHL_INT0_DWS_LOST_MSK)
1454 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1458 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1459 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1463 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1467 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1469 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)