Lines Matching defs:cr

139 	u16 cr;
255 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
261 cr &= ~STM32_RTC_CR_OSEL;
262 cr |= STM32_RTC_CR_OSEL_ALARM_A;
263 cr &= ~STM32_RTC_CR_TAMPOE;
264 cr &= ~STM32_RTC_CR_COE;
265 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE;
269 cr &= ~STM32_RTC_CR_OUT2EN;
273 cr |= STM32_RTC_CR_OUT2EN;
277 cr |= STM32_RTC_CR_OUT2EN;
285 writel_relaxed(cr, rtc->base + regs.cr);
296 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
303 if ((!(cr & STM32_RTC_CR_OUT2EN) &&
304 ((cr & calib) || cr & tampalrm)) ||
305 ((cr & calib) && (cr & tampalrm)))
309 if ((cr & STM32_RTC_CR_OUT2EN) &&
311 ((cr & calib) || (cr & tampalrm)))
466 unsigned int status, cr;
471 cr = readl_relaxed(rtc->base + regs->cr);
474 (cr & STM32_RTC_CR_ALRAIE)) {
598 unsigned int alrmar, cr, status;
601 cr = readl_relaxed(rtc->base + regs->cr);
654 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
665 unsigned int cr;
667 cr = readl_relaxed(rtc->base + regs->cr);
673 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
675 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
676 writel_relaxed(cr, rtc->base + regs->cr);
729 unsigned int cr, isr, alrmar;
759 cr = readl_relaxed(rtc->base + regs->cr);
760 cr &= ~STM32_RTC_CR_ALRAE;
761 writel_relaxed(cr, rtc->base + regs->cr);
815 .cr = 0x08,
841 .cr = 0x08,
876 .cr = 0x18,
902 .cr = 0x18,
930 unsigned int cr = readl_relaxed(rtc->base + regs.cr);
932 cr &= ~STM32_RTC_CR_OSEL;
933 cr &= ~STM32_RTC_CR_TAMPOE;
934 cr &= ~STM32_RTC_CR_COE;
935 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE;
936 cr &= ~STM32_RTC_CR_OUT2EN;
939 writel_relaxed(cr, rtc->base + regs.cr);
974 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
1018 cr = readl_relaxed(rtc->base + regs->cr);
1029 if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a))
1045 cr &= ~STM32_RTC_CR_FMT;
1046 writel_relaxed(cr, rtc->base + regs->cr);
1218 unsigned int cr;
1225 cr = readl_relaxed(rtc->base + regs->cr);
1226 cr &= ~STM32_RTC_CR_ALRAIE;
1227 writel_relaxed(cr, rtc->base + regs->cr);