drivers/pwm/pwm-sophgo-sg2042.c

69 static void pwm_sg2042_config(struct sg2042_pwm_ddata *ddata, unsigned int chan,
72 	void __iomem *base = ddata->base;
81 	struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
89 	period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX);
90 	hlperiod_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycle, NSEC_PER_SEC), U32_MAX);
95 	pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks);
101 	struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
107 		pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0);
119 	struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
124 	period_ticks = readl(ddata->base + SG2042_PWM_PERIOD(chan));
125 	hlperiod_ticks = readl(ddata->base + SG2042_PWM_HLPERIOD(chan));
136 	state->period = DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddata->clk_rate_hz);
137 	state->duty_cycle = DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC, ddata->clk_rate_hz);
143 static void pwm_sg2044_set_outputen(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
148 	pwmstart = readl(ddata->base + SG2044_PWM_PWMSTART);
155 	writel(pwmstart, ddata->base + SG2044_PWM_PWMSTART);
158 static void pwm_sg2044_set_outputdir(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
163 	pwm_oe = readl(ddata->base + SG2044_PWM_OE);
170 	writel(pwm_oe, ddata->base + SG2044_PWM_OE);
173 static void pwm_sg2044_set_polarity(struct sg2042_pwm_ddata *ddata, struct pwm_device *pwm,
178 	pwm_polarity = readl(ddata->base + SG2044_PWM_POLARITY);
185 	writel(pwm_polarity, ddata->base + SG2044_PWM_POLARITY);
191 	struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip);
193 	pwm_sg2044_set_polarity(ddata, pwm, state);
200 	pwm_sg2044_set_outputen(ddata, pwm, false);
205 	pwm_sg2044_set_outputdir(ddata, pwm, true);
206 	pwm_sg2044_set_outputen(ddata, pwm, true);
242 	struct sg2042_pwm_ddata *ddata;
252 	chip = devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata));
255 	ddata = pwmchip_get_drvdata(chip);
257 	ddata->base = devm_platform_ioremap_resource(pdev, 0);
258 	if (IS_ERR(ddata->base))
259 		return PTR_ERR(ddata->base);
269 	ddata->clk_rate_hz = clk_get_rate(clk);
271 	if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
273 				     "Invalid clock rate: %lu\n", ddata->clk_rate_hz);