Lines Matching defs:period

73 	u32 clk_div, period, high_width, value;
108 	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
109 	 * Calculate proper div value to keep period value in the bound.
111 	 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
114 	 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
118 	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
129 	period = mul_u64_u64_div_u64(state->period, rate, div);
130 	if (period > 0)
131 		period--;
134 	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
177 	u64 rate, period, high_width;
210 	period = FIELD_GET(PWM_PERIOD_MASK, con1);
212 	 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
213 	 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
215 	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);