Lines Matching defs:mchp_core_pwm
71 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
82 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
86 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
87 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
88 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
95 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))
96 mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
99 static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,
110 if (mchp_core_pwm->sync_update_mask & (1 << channel)) {
115 remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,
152 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
178 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
179 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
274 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
291 clk_rate = clk_get_rate(mchp_core_pwm->clk);
308 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
314 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
315 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
346 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
347 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
360 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
362 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
370 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
375 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
377 if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
382 rate = clk_get_rate(mchp_core_pwm->clk);
397 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
398 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
404 posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
405 negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
437 struct mchp_core_pwm_chip *mchp_core_pwm;
441 chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));
444 mchp_core_pwm = to_mchp_core_pwm(chip);
446 mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
447 if (IS_ERR(mchp_core_pwm->base))
448 return PTR_ERR(mchp_core_pwm->base);
450 mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
451 if (IS_ERR(mchp_core_pwm->clk))
452 return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),
456 &mchp_core_pwm->sync_update_mask))
457 mchp_core_pwm->sync_update_mask = 0;
461 mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
462 mchp_core_pwm->channel_enabled |=
463 readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
469 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
470 mchp_core_pwm->update_timestamp = ktime_get();