pinctrl/tegra/pinctrl-tegra-xusb.c

96 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
99 	writel(value, padctl->regs + offset);
102 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
105 	return readl(padctl->regs + offset);
110 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
112 	return padctl->soc->num_pins;
118 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
120 	return padctl->soc->pins[group].name;
153 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
185 		err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
203 	err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
210 			err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
218 			err = pinctrl_utils_add_map_configs(padctl->pinctrl,
239 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
247 		err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
267 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
269 	return padctl->soc->num_functions;
276 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
278 	return padctl->soc->functions[function].name;
286 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
288 	*num_groups = padctl->soc->functions[function].num_groups;
289 	*groups = padctl->soc->functions[function].groups;
298 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
303 	lane = &padctl->soc->lanes[group];
312 	value = padctl_readl(padctl, lane->offset);
315 	padctl_writel(padctl, value, lane->offset);
331 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
337 	lane = &padctl->soc->lanes[group];
345 		value = padctl_readl(padctl, lane->offset);
356 		dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
369 	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
376 	lane = &padctl->soc->lanes[group];
388 			regval = padctl_readl(padctl, lane->offset);
395 			padctl_writel(padctl, regval, lane->offset);
399 			dev_err(padctl->dev,
477 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
481 	mutex_lock(&padctl->lock);
483 	if (padctl->enable++ > 0)
486 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
488 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
492 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
494 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
498 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
500 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
503 	mutex_unlock(&padctl->lock);
507 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
511 	mutex_lock(&padctl->lock);
513 	if (WARN_ON(padctl->enable == 0))
516 	if (--padctl->enable > 0)
519 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
521 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
525 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
527 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
531 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
533 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
536 	mutex_unlock(&padctl->lock);
542 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
544 	return tegra_xusb_padctl_enable(padctl);
549 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
551 	return tegra_xusb_padctl_disable(padctl);
556 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
561 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
563 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
565 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
569 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
571 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
573 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
578 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
592 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
595 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
597 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
612 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
617 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
620 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
622 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
625 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
627 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
629 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
631 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
633 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
638 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
652 	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
655 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
657 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
659 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
661 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
663 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
666 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
668 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
671 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
687 	struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
693 	if (index >= ARRAY_SIZE(padctl->phys))
696 	return padctl->phys[index];
863 	{ .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
874 	struct tegra_xusb_padctl *padctl;
879 	padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
880 	if (!padctl)
883 	platform_set_drvdata(pdev, padctl);
884 	mutex_init(&padctl->lock);
885 	padctl->dev = &pdev->dev;
894 	padctl->soc = match->data;
896 	padctl->regs = devm_platform_ioremap_resource(pdev, 0);
897 	if (IS_ERR(padctl->regs))
898 		return PTR_ERR(padctl->regs);
900 	padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
901 	if (IS_ERR(padctl->rst))
902 		return PTR_ERR(padctl->rst);
904 	err = reset_control_deassert(padctl->rst);
908 	memset(&padctl->desc, 0, sizeof(padctl->desc));
909 	padctl->desc.name = dev_name(padctl->dev);
910 	padctl->desc.pins = tegra124_pins;
911 	padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
912 	padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
913 	padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
914 	padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
915 	padctl->desc.owner = THIS_MODULE;
917 	padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
918 						padctl);
919 	if (IS_ERR(padctl->pinctrl)) {
921 		err = PTR_ERR(padctl->pinctrl);
931 	padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
932 	phy_set_drvdata(phy, padctl);
940 	padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
941 	phy_set_drvdata(phy, padctl);
943 	padctl->provider = devm_of_phy_provider_register(&pdev->dev,
945 	if (IS_ERR(padctl->provider)) {
946 		err = PTR_ERR(padctl->provider);
954 	reset_control_assert(padctl->rst);
961 	struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
964 	err = reset_control_assert(padctl->rst);