pinctrl/qcom/pinctrl-msm.c

86 			    const struct msm_pingroup *g) \
88 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
91 			      const struct msm_pingroup *g) \
93 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
103 				const struct msm_pingroup *g)
105 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
107 	msm_writel_intr_status(val, pctrl, g);
190 	const struct msm_pingroup *g;
195 	g = &pctrl->soc->groups[group];
196 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
198 	for (i = 0; i < g->nfuncs; i++) {
199 		if (g->funcs[i] == function)
203 	if (WARN_ON(i == g->nfuncs))
222 	val = msm_readl_ctl(pctrl, g);
230 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&
232 		u32 io_val = msm_readl_io(pctrl, g);
234 		if (io_val & BIT(g->in_bit)) {
235 			if (!(io_val & BIT(g->out_bit)))
236 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);
238 			if (io_val & BIT(g->out_bit))
239 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);
244 		if (val & BIT(g->egpio_present))
245 			val &= ~BIT(g->egpio_enable);
248 		val |= i << g->mux_bit;
250 		if (egpio_func && val & BIT(g->egpio_present))
251 			val |= BIT(g->egpio_enable);
254 	msm_writel_ctl(val, pctrl, g);
267 			msm_ack_intr_status(pctrl, g);
280 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
283 	if (!g->nfuncs)
286 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
299 			  const struct msm_pingroup *g,
309 		*bit = g->pull_bit;
311 		if (g->i2c_pull_bit)
312 			*mask |= BIT(g->i2c_pull_bit) >> *bit;
315 		*bit = g->od_bit;
319 		*bit = g->drv_bit;
325 		*bit = g->oe_bit;
351 	const struct msm_pingroup *g;
364 	g = &pctrl->soc->groups[group];
366 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
370 	val = msm_readl_ctl(pctrl, g);
396 		else if (arg & BIT(g->i2c_pull_bit))
417 		val = msm_readl_io(pctrl, g);
418 		arg = !!(val & BIT(g->in_bit));
438 	const struct msm_pingroup *g;
449 	g = &pctrl->soc->groups[group];
455 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
476 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)
477 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;
494 			val = msm_readl_io(pctrl, g);
496 				val |= BIT(g->out_bit);
498 				val &= ~BIT(g->out_bit);
499 			msm_writel_io(val, pctrl, g);
549 		val = msm_readl_ctl(pctrl, g);
552 		msm_writel_ctl(val, pctrl, g);
567 	const struct msm_pingroup *g;
572 	g = &pctrl->soc->groups[offset];
576 	val = msm_readl_ctl(pctrl, g);
577 	val &= ~BIT(g->oe_bit);
578 	msm_writel_ctl(val, pctrl, g);
587 	const struct msm_pingroup *g;
592 	g = &pctrl->soc->groups[offset];
596 	val = msm_readl_io(pctrl, g);
598 		val |= BIT(g->out_bit);
600 		val &= ~BIT(g->out_bit);
601 	msm_writel_io(val, pctrl, g);
603 	val = msm_readl_ctl(pctrl, g);
604 	val |= BIT(g->oe_bit);
605 	msm_writel_ctl(val, pctrl, g);
615 	const struct msm_pingroup *g;
618 	g = &pctrl->soc->groups[offset];
620 	val = msm_readl_ctl(pctrl, g);
622 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
628 	const struct msm_pingroup *g;
632 	g = &pctrl->soc->groups[offset];
634 	val = msm_readl_io(pctrl, g);
635 	return !!(val & BIT(g->in_bit));
640 	const struct msm_pingroup *g;
645 	g = &pctrl->soc->groups[offset];
649 	val = msm_readl_io(pctrl, g);
651 		val |= BIT(g->out_bit);
653 		val &= ~BIT(g->out_bit);
654 	msm_writel_io(val, pctrl, g);
669 	const struct msm_pingroup *g;
695 	g = &pctrl->soc->groups[offset];
696 	ctl_reg = msm_readl_ctl(pctrl, g);
697 	io_reg = msm_readl_io(pctrl, g);
699 	is_out = !!(ctl_reg & BIT(g->oe_bit));
700 	func = (ctl_reg >> g->mux_bit) & 7;
701 	drive = (ctl_reg >> g->drv_bit) & 7;
702 	pull = (ctl_reg >> g->pull_bit) & 3;
704 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
705 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
708 		val = !!(io_reg & BIT(g->out_bit));
710 		val = !!(io_reg & BIT(g->in_bit));
713 		seq_printf(s, " %-8s: egpio\n", g->grp.name);
717 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
822 					  const struct msm_pingroup *g,
830 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
832 		pol = msm_readl_intr_cfg(pctrl, g);
833 		pol ^= BIT(g->intr_polarity_bit);
834 		msm_writel_intr_cfg(pol, pctrl, g);
836 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
837 		intstat = msm_readl_intr_status(pctrl, g);
849 	const struct msm_pingroup *g;
859 	g = &pctrl->soc->groups[d->hwirq];
863 	val = msm_readl_intr_cfg(pctrl, g);
885 		val &= ~BIT(g->intr_raw_status_bit);
887 	val &= ~BIT(g->intr_enable_bit);
888 	msm_writel_intr_cfg(val, pctrl, g);
899 	const struct msm_pingroup *g;
909 	g = &pctrl->soc->groups[d->hwirq];
913 	val = msm_readl_intr_cfg(pctrl, g);
914 	val |= BIT(g->intr_raw_status_bit);
915 	val |= BIT(g->intr_enable_bit);
916 	msm_writel_intr_cfg(val, pctrl, g);
964 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
970 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
983 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
1001 	const struct msm_pingroup *g;
1010 	g = &pctrl->soc->groups[d->hwirq];
1014 	msm_ack_intr_status(pctrl, g);
1017 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1046 	const struct msm_pingroup *g;
1052 		g = &pctrl->soc->groups[i];
1054 		if (g->intr_detection_width != 1 &&
1055 		    g->intr_detection_width != 2)
1064 	const struct msm_pingroup *g;
1085 	g = &pctrl->soc->groups[d->hwirq];
1092 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
1101 	if (g->intr_target_width)
1102 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
1105 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1109 		val &= ~(intr_target_mask << g->intr_target_bit);
1110 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1118 		val = msm_readl_intr_target(pctrl, g);
1119 		val &= ~(intr_target_mask << g->intr_target_bit);
1120 		val |= g->intr_target_kpss_val << g->intr_target_bit;
1121 		msm_writel_intr_target(val, pctrl, g);
1129 	val = oldval = msm_readl_intr_cfg(pctrl, g);
1130 	val |= BIT(g->intr_raw_status_bit);
1131 	if (g->intr_detection_width == 2) {
1132 		val &= ~(3 << g->intr_detection_bit);
1133 		val &= ~(1 << g->intr_polarity_bit);
1136 			val |= 1 << g->intr_detection_bit;
1137 			val |= BIT(g->intr_polarity_bit);
1140 			val |= 2 << g->intr_detection_bit;
1141 			val |= BIT(g->intr_polarity_bit);
1144 			val |= 3 << g->intr_detection_bit;
1145 			val |= BIT(g->intr_polarity_bit);
1150 			val |= BIT(g->intr_polarity_bit);
1153 	} else if (g->intr_detection_width == 1) {
1154 		val &= ~(1 << g->intr_detection_bit);
1155 		val &= ~(1 << g->intr_polarity_bit);
1158 			val |= BIT(g->intr_detection_bit);
1159 			val |= BIT(g->intr_polarity_bit);
1162 			val |= BIT(g->intr_detection_bit);
1165 			val |= BIT(g->intr_detection_bit);
1166 			val |= BIT(g->intr_polarity_bit);
1171 			val |= BIT(g->intr_polarity_bit);
1177 	msm_writel_intr_cfg(val, pctrl, g);
1187 		msm_ack_intr_status(pctrl, g);
1190 		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1223 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1258 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1263 		intr_cfg = msm_readl_intr_cfg(pctrl, g);
1264 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1265 			intr_cfg |= BIT(g->intr_wakeup_enable_bit);
1266 			msm_writel_intr_cfg(intr_cfg, pctrl, g);
1282 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1286 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1291 		intr_cfg = msm_readl_intr_cfg(pctrl, g);
1292 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1293 			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);
1294 			msm_writel_intr_cfg(intr_cfg, pctrl, g);
1330 	const struct msm_pingroup *g;
1344 		g = &pctrl->soc->groups[i];
1345 		val = msm_readl_intr_status(pctrl, g);
1346 		if (val & BIT(g->intr_status_bit)) {