Lines Matching refs:pcs

205 #define PCS_QUIRK_HAS_SHARED_IRQ	(pcs->flags & PCS_QUIRK_SHARED_IRQ)
206 #define PCS_HAS_IRQ		(pcs->flags & PCS_FEAT_IRQ)
207 #define PCS_HAS_PINCONF		(pcs->flags & PCS_FEAT_PINCONF)
268 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
271 	unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
273 	if (pcs->bits_per_mux) {
276 		pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
283 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
286 	return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
293 	struct pcs_device *pcs;
298 	pcs = pinctrl_dev_get_drvdata(pctldev);
300 	offset = pcs_pin_reg_offset_get(pcs, pin);
301 	val = pcs->read(pcs->base + offset);
303 	if (pcs->bits_per_mux)
304 		val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
306 	pa = pcs->res->start + offset;
314 	struct pcs_device *pcs;
316 	pcs = pinctrl_dev_get_drvdata(pctldev);
317 	devm_kfree(pcs->dev, map);
336 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
352 		dev_err(pcs->dev, "%s could not find function%i\n",
362 	struct pcs_device *pcs;
367 	pcs = pinctrl_dev_get_drvdata(pctldev);
369 	if (!pcs->fmask)
378 	dev_dbg(pcs->dev, "enabling %s function%i\n",
387 		raw_spin_lock_irqsave(&pcs->lock, flags);
388 		val = pcs->read(vals->reg);
390 		if (pcs->bits_per_mux)
393 			mask = pcs->fmask;
397 		pcs->write(val, vals->reg);
398 		raw_spin_unlock_irqrestore(&pcs->lock, flags);
407 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
413 	if (!pcs->fmask)
416 	list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
424 		offset = pcs_pin_reg_offset_get(pcs, pin);
426 		if (pcs->bits_per_mux) {
427 			int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
429 			data = pcs->read(pcs->base + offset);
430 			data &= ~(pcs->fmask << pin_shift);
432 			pcs->write(data, pcs->base + offset);
434 			data = pcs->read(pcs->base + offset);
435 			data &= ~pcs->fmask;
437 			pcs->write(data, pcs->base + offset);
485 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
507 		offset = pin * (pcs->width / BITS_PER_BYTE);
508 		data = pcs->read(pcs->base + offset) & func->conf[i].mask;
550 	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
575 			offset = pin * (pcs->width / BITS_PER_BYTE);
576 			data = pcs->read(pcs->base + offset);
605 			pcs->write(data, pcs->base + offset);
685  * @pcs: pcs driver instance
688 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
690 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
694 	i = pcs->pins.cur;
695 	if (i >= pcs->desc.npins) {
696 		dev_err(pcs->dev, "too many pins, max %i\n",
697 			pcs->desc.npins);
704 		val = pcs->read(pcs->base + offset);
706 			dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
707 				(unsigned long)pcs->res->start + offset, val);
709 			pcs->write(val, pcs->base + offset);
713 	pin = &pcs->pins.pa[i];
715 	pcs->pins.cur++;
722  * @pcs: pcs driver instance
729 static int pcs_allocate_pin_table(struct pcs_device *pcs)
733 	mux_bytes = pcs->width / BITS_PER_BYTE;
735 	if (pcs->bits_per_mux && pcs->fmask) {
736 		pcs->bits_per_pin = fls(pcs->fmask);
737 		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
739 		nr_pins = pcs->size / mux_bytes;
742 	dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
743 	pcs->pins.pa = devm_kcalloc(pcs->dev,
744 				nr_pins, sizeof(*pcs->pins.pa),
746 	if (!pcs->pins.pa)
749 	pcs->desc.pins = pcs->pins.pa;
750 	pcs->desc.npins = nr_pins;
752 	for (i = 0; i < pcs->desc.npins; i++) {
756 		offset = pcs_pin_reg_offset_get(pcs, i);
757 		res = pcs_add_pin(pcs, offset);
759 			dev_err(pcs->dev, "error adding pins: %i\n", res);
769  * @pcs: pcs driver instance
779 static int pcs_add_function(struct pcs_device *pcs,
790 	function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
798 	selector = pinmux_generic_add_function(pcs->pctl, name,
802 		devm_kfree(pcs->dev, function);
813  * @pcs: pcs driver instance
818 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
822 	if (offset >= pcs->size) {
823 		dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
824 			offset, pcs->size);
828 	if (pcs->bits_per_mux)
829 		index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
831 		index = offset / (pcs->width / BITS_PER_BYTE);
872 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
891 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
903 		dev_err(pcs->dev, "mask field of the property can't be 0\n");
911 		dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
916 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
955 	func->conf = devm_kcalloc(pcs->dev,
963 	settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
970 		pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
973 		pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
984  * @pcs: pinctrl driver instance
1001 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1014 		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1018 	vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1022 	pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1036 			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1042 		vals[found].reg = pcs->base + offset;
1053 		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1056 		pin = pcs_get_pin_by_offset(pcs, offset);
1058 			dev_err(pcs->dev,
1067 	mutex_lock(&pcs->mutex);
1068 	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1075 	gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1086 		res = pcs_parse_pinconf(pcs, np, function, map);
1096 	mutex_unlock(&pcs->mutex);
1101 	pinctrl_generic_remove_group(pcs->pctl, gsel);
1104 	pinmux_generic_remove_function(pcs->pctl, fsel);
1106 	mutex_unlock(&pcs->mutex);
1107 	devm_kfree(pcs->dev, pins);
1110 	devm_kfree(pcs->dev, vals);
1115 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1129 		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1134 		dev_err(pcs->dev, "pinconf not supported\n");
1138 	npins_in_row = pcs->width / pcs->bits_per_pin;
1140 	vals = devm_kzalloc(pcs->dev,
1146 	pins = devm_kzalloc(pcs->dev,
1164 			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1174 		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1180 			pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1181 			mask_pos = ((pcs->fmask) << bit_pos);
1186 				dev_err(pcs->dev,
1195 				dev_warn(pcs->dev,
1202 			vals[found].reg = pcs->base + offset;
1205 			pin = pcs_get_pin_by_offset(pcs, offset);
1207 				dev_err(pcs->dev,
1217 	mutex_lock(&pcs->mutex);
1218 	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1225 	res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1234 	mutex_unlock(&pcs->mutex);
1239 	pinmux_generic_remove_function(pcs->pctl, fsel);
1241 	mutex_unlock(&pcs->mutex);
1242 	devm_kfree(pcs->dev, pins);
1245 	devm_kfree(pcs->dev, vals);
1260 	struct pcs_device *pcs;
1264 	pcs = pinctrl_dev_get_drvdata(pctldev);
1267 	*map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1273 	pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1279 	if (pcs->bits_per_mux) {
1280 		ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1283 			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1288 		ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1291 			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1300 	devm_kfree(pcs->dev, pgnames);
1302 	devm_kfree(pcs->dev, *map);
1309  * @pcs: pcs driver instance
1311 static void pcs_irq_free(struct pcs_device *pcs)
1313 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1318 	if (pcs->domain)
1319 		irq_domain_remove(pcs->domain);
1329  * @pcs: pcs driver instance
1331 static void pcs_free_resources(struct pcs_device *pcs)
1333 	pcs_irq_free(pcs);
1336 	if (pcs->missing_nr_pinctrl_cells)
1337 		of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1341 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1357 		range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1365 		mutex_lock(&pcs->mutex);
1366 		list_add_tail(&range->node, &pcs->gpiofuncs);
1367 		mutex_unlock(&pcs->mutex);
1398 	struct pcs_device *pcs;
1402 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1403 	list_for_each(pos, &pcs->irqs) {
1412 		raw_spin_lock(&pcs->lock);
1413 		mask = pcs->read(pcswi->reg);
1418 		pcs->write(mask, pcswi->reg);
1421 		mask = pcs->read(pcswi->reg);
1422 		raw_spin_unlock(&pcs->lock);
1479 	struct pcs_device *pcs;
1483 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1484 	list_for_each(pos, &pcs->irqs) {
1489 		raw_spin_lock(&pcs->lock);
1490 		mask = pcs->read(pcswi->reg);
1491 		raw_spin_unlock(&pcs->lock);
1493 			generic_handle_domain_irq(pcs->domain,
1540 	struct pcs_device *pcs;
1543 	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1544 	pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1548 	pcswi->reg = pcs->base + hwirq;
1552 	mutex_lock(&pcs->mutex);
1553 	list_add_tail(&pcswi->node, &pcs->irqs);
1554 	mutex_unlock(&pcs->mutex);
1557 	irq_set_chip_and_handler(irq, &pcs->chip,
1572  * @pcs: pcs driver instance
1575 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1578 	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1588 	INIT_LIST_HEAD(&pcs->irqs);
1589 	pcs->chip.name = name;
1590 	pcs->chip.irq_ack = pcs_irq_mask;
1591 	pcs->chip.irq_mask = pcs_irq_mask;
1592 	pcs->chip.irq_unmask = pcs_irq_unmask;
1593 	pcs->chip.irq_set_wake = pcs_irq_set_wake;
1618 	num_irqs = pcs->size;
1620 	pcs->domain = irq_domain_create_simple(of_fwnode_handle(np),
1624 	if (!pcs->domain) {
1632 static int pcs_save_context(struct pcs_device *pcs)
1639 	mux_bytes = pcs->width / BITS_PER_BYTE;
1641 	if (!pcs->saved_vals) {
1642 		pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1643 		if (!pcs->saved_vals)
1647 	switch (pcs->width) {
1649 		regsl = pcs->saved_vals;
1650 		for (i = 0; i < pcs->size; i += mux_bytes)
1651 			*regsl++ = pcs->read(pcs->base + i);
1654 		regsw = pcs->saved_vals;
1655 		for (i = 0; i < pcs->size; i += mux_bytes)
1656 			*regsw++ = pcs->read(pcs->base + i);
1659 		regshw = pcs->saved_vals;
1660 		for (i = 0; i < pcs->size; i += mux_bytes)
1661 			*regshw++ = pcs->read(pcs->base + i);
1668 static void pcs_restore_context(struct pcs_device *pcs)
1675 	mux_bytes = pcs->width / BITS_PER_BYTE;
1677 	switch (pcs->width) {
1679 		regsl = pcs->saved_vals;
1680 		for (i = 0; i < pcs->size; i += mux_bytes)
1681 			pcs->write(*regsl++, pcs->base + i);
1684 		regsw = pcs->saved_vals;
1685 		for (i = 0; i < pcs->size; i += mux_bytes)
1686 			pcs->write(*regsw++, pcs->base + i);
1689 		regshw = pcs->saved_vals;
1690 		for (i = 0; i < pcs->size; i += mux_bytes)
1691 			pcs->write(*regshw++, pcs->base + i);
1698 	struct pcs_device *pcs = dev_get_drvdata(dev);
1700 	if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1703 		ret = pcs_save_context(pcs);
1708 	return pinctrl_force_sleep(pcs->pctl);
1713 	struct pcs_device *pcs = dev_get_drvdata(dev);
1715 	if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1716 		pcs_restore_context(pcs);
1718 	return pinctrl_force_default(pcs->pctl);
1727  * @pcs: pinctrl driver instance
1735 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1748 	dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1751 	p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1756 	p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1761 	p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1765 	pcs->missing_nr_pinctrl_cells = p;
1768 	error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1779 	struct pcs_device *pcs;
1787 	pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1788 	if (!pcs)
1791 	pcs->dev = &pdev->dev;
1792 	pcs->np = np;
1793 	raw_spin_lock_init(&pcs->lock);
1794 	mutex_init(&pcs->mutex);
1795 	INIT_LIST_HEAD(&pcs->gpiofuncs);
1796 	pcs->flags = soc->flags;
1797 	memcpy(&pcs->socdata, soc, sizeof(*soc));
1800 				   &pcs->width);
1802 		dev_err(pcs->dev, "register width not specified\n");
1808 				   &pcs->fmask);
1810 		pcs->fshift = __ffs(pcs->fmask);
1811 		pcs->fmax = pcs->fmask >> pcs->fshift;
1814 		pcs->fmask = 0;
1815 		pcs->fshift = 0;
1816 		pcs->fmax = 0;
1820 					&pcs->foff);
1822 		pcs->foff = PCS_OFF_DISABLED;
1824 	pcs->bits_per_mux = of_property_read_bool(np,
1826 	ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1827 					      pcs->bits_per_mux ? 2 : 1);
1836 		dev_err(pcs->dev, "could not get resource\n");
1840 	pcs->res = devm_request_mem_region(pcs->dev, res->start,
1842 	if (!pcs->res) {
1843 		dev_err(pcs->dev, "could not get mem_region\n");
1847 	pcs->size = resource_size(pcs->res);
1848 	pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1849 	if (!pcs->base) {
1850 		dev_err(pcs->dev, "could not ioremap\n");
1854 	platform_set_drvdata(pdev, pcs);
1856 	switch (pcs->width) {
1858 		pcs->read = pcs_readb;
1859 		pcs->write = pcs_writeb;
1862 		pcs->read = pcs_readw;
1863 		pcs->write = pcs_writew;
1866 		pcs->read = pcs_readl;
1867 		pcs->write = pcs_writel;
1873 	pcs->desc.name = DRIVER_NAME;
1874 	pcs->desc.pctlops = &pcs_pinctrl_ops;
1875 	pcs->desc.pmxops = &pcs_pinmux_ops;
1877 		pcs->desc.confops = &pcs_pinconf_ops;
1878 	pcs->desc.owner = THIS_MODULE;
1880 	ret = pcs_allocate_pin_table(pcs);
1884 	ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);
1886 		dev_err(pcs->dev, "could not register single pinctrl driver\n");
1890 	ret = pcs_add_gpio_func(np, pcs);
1894 	pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1895 	if (pcs->socdata.irq)
1896 		pcs->flags |= PCS_FEAT_IRQ;
1902 			pcs->socdata.rearm = pdata->rearm;
1904 			pcs->socdata.irq = pdata->irq;
1905 			pcs->flags |= PCS_FEAT_IRQ;
1910 		ret = pcs_irq_init_chained_handler(pcs, np);
1912 			dev_warn(pcs->dev, "initialized with no interrupts\n");
1915 	dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1917 	ret = pinctrl_enable(pcs->pctl);
1923 	pcs_free_resources(pcs);
1930 	struct pcs_device *pcs = platform_get_drvdata(pdev);
1932 	pcs_free_resources(pcs);