pinctrl/bcm/pinctrl-ns2-mux.c

16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
22 #include "../pinctrl-utils.h"
100  * Northstar2 IOMUX pinctrl core
497 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
499 	return pinctrl->num_groups;
505 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
507 	return pinctrl->groups[selector].name;
514 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
516 	*pins = pinctrl->groups[selector].pins;
517 	*num_pins = pinctrl->groups[selector].num_pins;
539 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
541 	return pinctrl->num_functions;
547 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
549 	return pinctrl->functions[selector].name;
557 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
559 	*groups = pinctrl->functions[selector].groups;
560 	*num_groups = pinctrl->functions[selector].num_groups;
565 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
591 			dev_err(pinctrl->dev,
593 			dev_err(pinctrl->dev, "func:%s grp:%s\n",
609 		base_address = pinctrl->base0;
613 		base_address = pinctrl->base1;
620 	spin_lock_irqsave(&pinctrl->lock, flags);
625 	spin_unlock_irqrestore(&pinctrl->lock, flags);
633 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
637 	if (grp_select >= pinctrl->num_groups ||
638 		func_select >= pinctrl->num_functions)
641 	func = &pinctrl->functions[func_select];
642 	grp = &pinctrl->groups[grp_select];
650 	return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
656 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
662 	base_address = pinctrl->pinconf_base;
663 	spin_lock_irqsave(&pinctrl->lock, flags);
671 	spin_unlock_irqrestore(&pinctrl->lock, flags);
679 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
684 	spin_lock_irqsave(&pinctrl->lock, flags);
685 	enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
688 	spin_unlock_irqrestore(&pinctrl->lock, flags);
702 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
708 	base_address = pinctrl->pinconf_base;
709 	spin_lock_irqsave(&pinctrl->lock, flags);
717 	spin_unlock_irqrestore(&pinctrl->lock, flags);
726 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
731 	spin_lock_irqsave(&pinctrl->lock, flags);
732 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
734 	spin_unlock_irqrestore(&pinctrl->lock, flags);
743 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
749 	base_address = pinctrl->pinconf_base;
750 	spin_lock_irqsave(&pinctrl->lock, flags);
759 	spin_unlock_irqrestore(&pinctrl->lock, flags);
770 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
775 	spin_lock_irqsave(&pinctrl->lock, flags);
776 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
786 	spin_unlock_irqrestore(&pinctrl->lock, flags);
792 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
802 	base_address = pinctrl->pinconf_base;
803 	spin_lock_irqsave(&pinctrl->lock, flags);
808 	spin_unlock_irqrestore(&pinctrl->lock, flags);
818 	struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
823 	spin_lock_irqsave(&pinctrl->lock, flags);
824 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
828 	spin_unlock_irqrestore(&pinctrl->lock, flags);
977 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
982 	pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
985 	if (!pinctrl->mux_log)
989 		pinctrl->mux_log[i].is_configured = false;
991 	log = &pinctrl->mux_log[0];
1003 		log = &pinctrl->mux_log[i];
1015 		log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1026 	struct ns2_pinctrl *pinctrl;
1031 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1032 	if (!pinctrl)
1035 	pinctrl->dev = &pdev->dev;
1036 	platform_set_drvdata(pdev, pinctrl);
1037 	spin_lock_init(&pinctrl->lock);
1039 	pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1040 	if (IS_ERR(pinctrl->base0))
1041 		return PTR_ERR(pinctrl->base0);
1046 	pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1048 	if (!pinctrl->base1) {
1053 	pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1054 	if (IS_ERR(pinctrl->pinconf_base))
1055 		return PTR_ERR(pinctrl->pinconf_base);
1057 	ret = ns2_mux_log_init(pinctrl);
1074 	pinctrl->groups = ns2_pin_groups;
1075 	pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1076 	pinctrl->functions = ns2_pin_functions;
1077 	pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1080 	pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1081 			pinctrl);
1082 	if (IS_ERR(pinctrl->pctl)) {
1083 		dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1084 		return PTR_ERR(pinctrl->pctl);