Lines Matching full:phy
3 * phy-ti-pipe3 - PIPE3 PHY driver.
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
300 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
305 rate = clk_get_rate(phy->sys_clk);
312 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
317 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
318 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
320 static int ti_pipe3_power_off(struct phy *x)
323 struct ti_pipe3 *phy = phy_get_drvdata(x);
325 if (!phy->phy_power_syscon) {
326 omap_control_phy_power(phy->control_dev, 0);
330 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
335 static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
337 static int ti_pipe3_power_on(struct phy *x)
342 struct ti_pipe3 *phy = phy_get_drvdata(x);
345 if (!phy->phy_power_syscon) {
346 omap_control_phy_power(phy->control_dev, 1);
350 rate = clk_get_rate(phy->sys_clk);
352 dev_err(phy->dev, "Invalid clock rate\n");
358 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
365 if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) {
372 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
377 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
381 if (phy->mode == PIPE3_MODE_PCIE)
382 ti_pipe3_calibrate(phy);
387 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
395 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
400 dev_err(phy->dev, "DPLL failed to lock\n");
404 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
409 dpll_params = ti_pipe3_get_dpll_params(phy);
413 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
416 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
418 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
421 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
423 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
426 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
428 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
431 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
433 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
436 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
438 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
440 return ti_pipe3_dpll_wait_lock(phy);
443 static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
446 struct pipe3_settings *s = &phy->settings;
448 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
451 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
453 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
466 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
468 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
471 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
473 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
476 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
478 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
486 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
488 if (phy->mode == PIPE3_MODE_SATA) {
489 val = ti_pipe3_readl(phy->phy_rx,
492 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
497 static int ti_pipe3_init(struct phy *x)
499 struct ti_pipe3 *phy = phy_get_drvdata(x);
503 ti_pipe3_enable_clocks(phy);
505 * Set pcie_pcs register to 0x96 for proper functioning of phy
509 if (phy->mode == PIPE3_MODE_PCIE) {
510 if (!phy->pcs_syscon) {
511 omap_control_pcie_pcs(phy->control_dev, 0x96);
516 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
522 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
525 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
526 ret = ti_pipe3_dpll_wait_lock(phy);
530 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
531 if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
535 ret = ti_pipe3_dpll_program(phy);
537 ti_pipe3_disable_clocks(phy);
541 ti_pipe3_calibrate(phy);
546 static int ti_pipe3_exit(struct phy *x)
548 struct ti_pipe3 *phy = phy_get_drvdata(x);
555 if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
559 if (phy->mode != PIPE3_MODE_PCIE) {
561 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
563 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
569 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
575 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
582 if (phy->mode == PIPE3_MODE_SATA) {
583 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
585 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
589 ti_pipe3_disable_clocks(phy);
603 static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
606 struct device *dev = phy->dev;
608 phy->refclk = devm_clk_get(dev, "refclk");
609 if (IS_ERR(phy->refclk)) {
611 /* older DTBs have missing refclk in SATA PHY
612 * so don't bail out in case of SATA PHY.
614 if (phy->mode != PIPE3_MODE_SATA)
615 return PTR_ERR(phy->refclk);
618 if (phy->mode != PIPE3_MODE_SATA) {
619 phy->wkupclk = devm_clk_get(dev, "wkupclk");
620 if (IS_ERR(phy->wkupclk)) {
622 return PTR_ERR(phy->wkupclk);
625 phy->wkupclk = ERR_PTR(-ENODEV);
628 if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
629 phy->sys_clk = devm_clk_get(dev, "sysclk");
630 if (IS_ERR(phy->sys_clk)) {
636 if (phy->mode == PIPE3_MODE_PCIE) {
651 clk = devm_clk_get(dev, "phy-div");
653 dev_err(dev, "unable to get phy-div clk\n");
658 phy->div_clk = devm_clk_get(dev, "div-clk");
659 if (IS_ERR(phy->div_clk)) {
661 return PTR_ERR(phy->div_clk);
664 phy->div_clk = ERR_PTR(-ENODEV);
670 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
672 struct device *dev = phy->dev;
677 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
678 "syscon-phy-power");
679 if (IS_ERR(phy->phy_power_syscon)) {
681 "can't get syscon-phy-power, using control device\n");
682 phy->phy_power_syscon = NULL;
685 "syscon-phy-power", 1,
686 &phy->power_reg)) {
692 if (!phy->phy_power_syscon) {
706 phy->control_dev = &control_pdev->dev;
709 if (phy->mode == PIPE3_MODE_PCIE) {
710 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
712 if (IS_ERR(phy->pcs_syscon)) {
715 phy->pcs_syscon = NULL;
719 &phy->pcie_pcs_reg)) {
727 if (phy->mode == PIPE3_MODE_SATA) {
728 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
730 if (IS_ERR(phy->dpll_reset_syscon)) {
733 phy->dpll_reset_syscon = NULL;
737 &phy->dpll_reset_reg)) {
748 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
750 struct device *dev = phy->dev;
753 phy->phy_rx = devm_platform_ioremap_resource_byname(pdev, "phy_rx");
754 if (IS_ERR(phy->phy_rx))
755 return PTR_ERR(phy->phy_rx);
757 phy->phy_tx = devm_platform_ioremap_resource_byname(pdev, "phy_tx");
759 return PTR_ERR_OR_ZERO(phy->phy_tx);
762 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
764 struct device *dev = phy->dev;
767 if (phy->mode == PIPE3_MODE_PCIE)
770 phy->pll_ctrl_base =
772 return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
777 struct ti_pipe3 *phy;
778 struct phy *generic_phy;
784 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
785 if (!phy)
792 phy->dev = dev;
793 phy->mode = data->mode;
794 phy->dpll_map = data->dpll_map;
795 phy->settings = data->settings;
797 ret = ti_pipe3_get_pll_base(phy);
801 ret = ti_pipe3_get_tx_rx_base(phy);
805 ret = ti_pipe3_get_sysctrl(phy);
809 ret = ti_pipe3_get_clk(phy);
813 platform_set_drvdata(pdev, phy);
817 * Prevent auto-disable of refclk for SATA PHY due to Errata i783
819 if (phy->mode == PIPE3_MODE_SATA) {
820 if (!IS_ERR(phy->refclk)) {
821 clk_prepare_enable(phy->refclk);
822 phy->sata_refclk_enabled = true;
830 phy_set_drvdata(generic_phy, phy);
840 struct ti_pipe3 *phy = platform_get_drvdata(pdev);
842 if (phy->mode == PIPE3_MODE_SATA) {
843 clk_disable_unprepare(phy->refclk);
844 phy->sata_refclk_enabled = false;
849 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
853 if (!IS_ERR(phy->refclk)) {
854 ret = clk_prepare_enable(phy->refclk);
856 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
861 if (!IS_ERR(phy->wkupclk)) {
862 ret = clk_prepare_enable(phy->wkupclk);
864 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
869 if (!IS_ERR(phy->div_clk)) {
870 ret = clk_prepare_enable(phy->div_clk);
872 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
880 if (!IS_ERR(phy->wkupclk))
881 clk_disable_unprepare(phy->wkupclk);
884 if (!IS_ERR(phy->refclk))
885 clk_disable_unprepare(phy->refclk);
890 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
892 if (!IS_ERR(phy->wkupclk))
893 clk_disable_unprepare(phy->wkupclk);
894 if (!IS_ERR(phy->refclk))
895 clk_disable_unprepare(phy->refclk);
896 if (!IS_ERR(phy->div_clk))
897 clk_disable_unprepare(phy->div_clk);
902 .compatible = "ti,phy-usb3",
910 .compatible = "ti,phy-pipe3-sata",
914 .compatible = "ti,phy-pipe3-pcie",
934 MODULE_DESCRIPTION("TI PIPE3 phy driver");