phy/tegra/xusb-tegra210.c

432 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
434 	return container_of(padctl, struct tegra210_xusb_padctl, base);
454 			dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",
463 /* must be called under padctl->lock */
464 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
466 	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
486 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
491 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
493 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
498 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
500 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
502 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
504 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
506 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
508 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
510 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
512 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
520 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
522 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
529 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
531 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
533 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
535 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
538 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
542 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
544 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
546 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
548 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
553 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
565 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
567 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
572 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
584 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
586 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
591 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
603 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
606 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
611 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
623 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
625 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
630 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
642 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
644 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
648 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
650 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
652 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
654 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
656 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
658 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
667 	for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
668 		value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
670 		padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
682 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
684 	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
693 	for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
694 		value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
696 		padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
702 /* must be called under padctl->lock */
703 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl)
705 	struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
706 	struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0);
732 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
737 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
739 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
744 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
746 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
748 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
750 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
752 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
754 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
756 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
758 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
773 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
775 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
788 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
790 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
792 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
794 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
797 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
801 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
803 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
805 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
807 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
812 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
824 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
826 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
831 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
843 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
845 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
850 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
862 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
865 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
870 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
882 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
884 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
889 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
901 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
903 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
907 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
909 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
911 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
913 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
915 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
917 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
926 	for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
927 		value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
929 		padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
941 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
943 	struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
952 	for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
953 		value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
955 		padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
961 static void tegra210_aux_mux_lp0_clamp_disable(struct tegra_xusb_padctl *padctl)
965 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
967 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
971 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
973 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
977 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
979 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
982 static void tegra210_aux_mux_lp0_clamp_enable(struct tegra_xusb_padctl *padctl)
986 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
988 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
992 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
994 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
998 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1000 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1003 static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
1005 	if (padctl->pcie)
1006 		tegra210_pex_uphy_enable(padctl);
1008 	if (padctl->sata)
1009 		tegra210_sata_uphy_enable(padctl);
1014 		dev_dbg(padctl->dev, "PLLE is already in HW control\n");
1016 	tegra210_aux_mux_lp0_clamp_disable(padctl);
1022 tegra210_uphy_deinit(struct tegra_xusb_padctl *padctl)
1024 	tegra210_aux_mux_lp0_clamp_enable(padctl);
1026 	if (padctl->sata)
1027 		tegra210_sata_uphy_disable(padctl);
1029 	if (padctl->pcie)
1030 		tegra210_pex_uphy_disable(padctl);
1033 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
1038 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1053 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1061 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1063 	struct device *dev = padctl->dev;
1071 	mutex_lock(&padctl->lock);
1073 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1075 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1079 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1081 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1085 	mutex_unlock(&padctl->lock);
1092 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1094 	struct device *dev = padctl->dev;
1102 	mutex_lock(&padctl->lock);
1104 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1106 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1110 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1112 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1114 	mutex_unlock(&padctl->lock);
1121 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1123 	struct device *dev = padctl->dev;
1131 	mutex_lock(&padctl->lock);
1133 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1136 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1140 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1143 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1145 	mutex_unlock(&padctl->lock);
1152 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1154 	struct device *dev = padctl->dev;
1162 	mutex_lock(&padctl->lock);
1164 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1167 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1171 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1174 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1176 	mutex_unlock(&padctl->lock);
1183 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1190 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1199 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1203 	mutex_lock(&padctl->lock);
1205 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1208 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1212 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1215 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1217 	mutex_unlock(&padctl->lock);
1224 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1228 	mutex_lock(&padctl->lock);
1230 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1233 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1237 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1240 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1242 	mutex_unlock(&padctl->lock);
1249 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1253 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1263 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1267 	mutex_lock(&padctl->lock);
1269 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1272 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1276 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1279 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1281 	mutex_unlock(&padctl->lock);
1288 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1292 	mutex_lock(&padctl->lock);
1294 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1297 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1301 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1304 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1306 	mutex_unlock(&padctl->lock);
1313 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1317 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1338 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1339 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1349 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1353 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));
1510 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1511 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1559 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1560 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1660 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1661 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1695 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
1702 	port = tegra_xusb_find_port(padctl, "usb3", index);
1708 	if (lane->pad == padctl->pcie)
1713 	value = padctl_readl(padctl, offset);
1727 	padctl_writel(padctl, value, offset);
1801 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1807 	port = tegra_xusb_find_usb2_port(padctl, index);
1819 	mutex_lock(&padctl->lock);
1821 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1826 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1828 	mutex_unlock(&padctl->lock);
1836 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1840 	port = tegra_xusb_find_usb2_port(padctl, lane->index);
1855 static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
1860 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
1862 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1874 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1879 static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
1884 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
1886 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1891 			padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1894 			value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1908 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1917 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1918 	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
1922 	mutex_lock(&padctl->lock);
1928 			tegra210_xusb_padctl_id_override(padctl, true);
1932 			tegra210_xusb_padctl_vbus_override(padctl, true);
1942 			tegra210_xusb_padctl_id_override(padctl, false);
1943 			tegra210_xusb_padctl_vbus_override(padctl, false);
1947 	mutex_unlock(&padctl->lock);
1957 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1964 	port = tegra_xusb_find_usb2_port(padctl, index);
1970 	priv = to_tegra210_xusb_padctl(padctl);
1972 	mutex_lock(&padctl->lock);
1975 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1980 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1982 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1985 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1989 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1992 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1996 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1999 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2002 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2015 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2017 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
2027 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
2029 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
2038 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
2040 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2052 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2054 	value = padctl_readl(padctl,
2064 	padctl_writel(padctl, value,
2069 		mutex_unlock(&padctl->lock);
2077 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2086 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2088 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2090 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2094 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2096 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2103 	mutex_unlock(&padctl->lock);
2108 	mutex_unlock(&padctl->lock);
2116 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2120 	port = tegra_xusb_find_usb2_port(padctl, lane->index);
2127 	mutex_lock(&padctl->lock);
2130 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2133 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2137 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2140 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2144 		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2147 		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2149 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2152 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2161 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2163 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2166 	mutex_unlock(&padctl->lock);
2180 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
2196 	err = tegra_xusb_pad_init(pad, padctl, np);
2297 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2300 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
2305 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
2320 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2329 	padctl_writel(padctl, hsic->strobe_trim,
2332 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2337 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2339 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2348 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2350 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2366 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2372 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2381 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2385 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2387 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2404 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2408 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2418 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2434 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
2450 	err = tegra_xusb_pad_init(pad, padctl, np);
2498 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2501 	value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2512 	padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2517 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2520 	value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2531 	padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2567 	if (!lane || !lane->pad || !lane->pad->padctl)
2574 	return tegra_xusb_find_usb3_port(lane->pad->padctl, port);
2581 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2593 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2602 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2604 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2609 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2611 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2616 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2618 	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
2621 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2626 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2628 	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
2631 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2633 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2637 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2639 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2643 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2645 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2654 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2666 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2668 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2672 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2674 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2678 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2680 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2732 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2734 	mutex_lock(&padctl->lock);
2736 	tegra210_uphy_init(padctl);
2738 	mutex_unlock(&padctl->lock);
2746 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2749 	mutex_lock(&padctl->lock);
2754 	mutex_unlock(&padctl->lock);
2761 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2764 	mutex_lock(&padctl->lock);
2769 	mutex_unlock(&padctl->lock);
2781 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
2797 	err = tegra_xusb_pad_init(pad, padctl, np);
2902 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2904 	mutex_lock(&padctl->lock);
2906 	tegra210_uphy_init(padctl);
2908 	mutex_unlock(&padctl->lock);
2915 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2918 	mutex_lock(&padctl->lock);
2923 	mutex_unlock(&padctl->lock);
2930 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2933 	mutex_lock(&padctl->lock);
2938 	mutex_unlock(&padctl->lock);
2950 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
2966 	err = tegra_xusb_pad_init(pad, padctl, np);
3031 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
3054 	return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
3088 	struct tegra_xusb_padctl *padctl;
3093 	padctl = lane->pad->padctl;
3095 	value = padctl_readl(padctl,
3100 		tegra210_xusb_padctl_vbus_override(padctl, false);
3101 		tegra210_xusb_padctl_vbus_override(padctl, true);
3144 	struct tegra210_xusb_padctl *padctl;
3149 	padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
3150 	if (!padctl)
3153 	padctl->base.dev = dev;
3154 	padctl->base.soc = soc;
3156 	err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
3175 	padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk");
3176 	if (!padctl->regmap)
3180 	return &padctl->base;
3183 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
3187 static void tegra210_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
3189 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
3192 		padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
3194 		padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
3196 		padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
3198 		padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
3201 static void tegra210_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
3203 	struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
3206 	padctl_writel(padctl, priv->context.usb2_pad_mux,
3208 	padctl_writel(padctl, priv->context.usb2_port_cap,
3210 	padctl_writel(padctl, priv->context.ss_port_map,
3213 	list_for_each_entry(lane, &padctl->lanes, list) {
3218 	padctl_writel(padctl, priv->context.usb3_pad_mux,
3221 	list_for_each_entry(lane, &padctl->lanes, list) {
3227 static int tegra210_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
3229 	mutex_lock(&padctl->lock);
3231 	tegra210_uphy_deinit(padctl);
3233 	tegra210_xusb_padctl_save(padctl);
3235 	mutex_unlock(&padctl->lock);
3239 static int tegra210_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
3241 	mutex_lock(&padctl->lock);
3243 	tegra210_xusb_padctl_restore(padctl);
3245 	tegra210_uphy_init(padctl);
3247 	mutex_unlock(&padctl->lock);