phy/tegra/xusb-tegra186.c

276 	/* padctl context */
291 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
293 	return container_of(padctl, struct tegra186_xusb_padctl, base);
333 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
334 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
338 	mutex_lock(&padctl->lock);
430 		if (padctl->soc->supports_lp_cfg_en)
439 		if (padctl->soc->supports_lp_cfg_en)
474 	mutex_unlock(&padctl->lock);
481 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
482 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
486 	mutex_lock(&padctl->lock);
505 	if (padctl->soc->supports_lp_cfg_en) {
522 	mutex_unlock(&padctl->lock);
529 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
533 	mutex_lock(&padctl->lock);
535 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
538 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
542 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
545 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
547 	mutex_unlock(&padctl->lock);
554 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
558 	mutex_lock(&padctl->lock);
560 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
563 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
567 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
570 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
572 	mutex_unlock(&padctl->lock);
579 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
583 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
601 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
603 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
604 	struct device *dev = padctl->dev;
615 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
620 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
622 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
626 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
630 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
632 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
634 	if (padctl->soc->poll_trk_completed) {
635 		err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
644 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
646 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
651 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
652 	if (padctl->soc->trk_update_on_idle)
654 	if (padctl->soc->trk_hw_mode)
656 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
658 	if (!padctl->soc->trk_hw_mode)
662 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
664 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
670 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
672 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
674 	if (padctl->soc->trk_hw_mode) {
675 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
677 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
686 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
687 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
689 	struct device *dev = padctl->dev;
696 	mutex_lock(&padctl->lock);
698 		mutex_unlock(&padctl->lock);
702 	port = tegra_xusb_find_usb2_port(padctl, index);
705 		mutex_unlock(&padctl->lock);
711 	tegra186_utmi_bias_pad_power_on(padctl);
715 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
717 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
719 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
721 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
724 	mutex_unlock(&padctl->lock);
730 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
731 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
738 	mutex_lock(&padctl->lock);
740 		mutex_unlock(&padctl->lock);
744 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
746 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
748 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
750 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
752 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
758 	tegra186_utmi_bias_pad_power_off(padctl);
760 	mutex_unlock(&padctl->lock);
763 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
768 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
770 	value = padctl_readl(padctl, USB2_VBUS_ID);
780 	padctl_writel(padctl, value, USB2_VBUS_ID);
785 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
791 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
793 	value = padctl_readl(padctl, USB2_VBUS_ID);
799 			padctl_writel(padctl, value, USB2_VBUS_ID);
802 			value = padctl_readl(padctl, USB2_VBUS_ID);
808 			padctl_writel(padctl, value, USB2_VBUS_ID);
812 				dev_err(padctl->dev, "Failed to enable regulator: %d\n", err);
824 				dev_err(padctl->dev, "Failed to disable regulator: %d\n", err);
830 			padctl_writel(padctl, value, USB2_VBUS_ID);
841 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
842 	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
846 	mutex_lock(&padctl->lock);
852 			err = tegra186_xusb_padctl_id_override(padctl, port, true);
856 			tegra186_xusb_padctl_vbus_override(padctl, true);
858 			err = tegra186_xusb_padctl_id_override(padctl, port, false);
861 			tegra186_xusb_padctl_vbus_override(padctl, false);
865 	mutex_unlock(&padctl->lock);
873 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
874 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
877 	struct device *dev = padctl->dev;
880 	port = tegra_xusb_find_usb2_port(padctl, index);
886 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
889 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
891 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
903 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
905 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
926 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
928 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
933 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
950 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
953 	struct device *dev = padctl->dev;
957 	port = tegra_xusb_find_usb2_port(padctl, index);
966 		reg = padctl_readl(padctl, USB2_VBUS_ID);
970 		padctl_writel(padctl, reg, USB2_VBUS_ID);
988 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
991 	struct device *dev = padctl->dev;
994 	port = tegra_xusb_find_usb2_port(padctl, index);
1022 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1026 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1039 	err = tegra_xusb_pad_init(pad, padctl, np);
1094 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1142 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1146 	mutex_lock(&padctl->lock);
1148 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1150 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1154 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1156 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1160 	mutex_unlock(&padctl->lock);
1167 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1171 	mutex_lock(&padctl->lock);
1173 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1175 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1179 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1181 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1183 	mutex_unlock(&padctl->lock);
1190 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1194 	mutex_lock(&padctl->lock);
1196 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1199 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1203 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1206 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1208 	mutex_unlock(&padctl->lock);
1215 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1219 	mutex_lock(&padctl->lock);
1221 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1224 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1228 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1231 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1233 	mutex_unlock(&padctl->lock);
1240 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1244 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1273 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1286 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1290 	struct device *dev = padctl->dev;
1293 	port = tegra_xusb_find_usb3_port(padctl, index);
1299 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1306 	mutex_lock(&padctl->lock);
1308 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1320 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1322 	if (padctl->soc->supports_gen2 && port->disable_gen2) {
1323 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1328 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1331 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1333 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1337 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1339 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1343 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1345 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1347 	mutex_unlock(&padctl->lock);
1355 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1358 	struct device *dev = padctl->dev;
1361 	port = tegra_xusb_find_usb3_port(padctl, index);
1367 	mutex_lock(&padctl->lock);
1369 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1371 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1375 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1377 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1381 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1383 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1385 	mutex_unlock(&padctl->lock);
1409 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1425 	err = tegra_xusb_pad_init(pad, padctl, np);
1462 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1464 	struct device *dev = padctl->base.dev;
1469 	count = padctl->base.soc->ports.usb2.count;
1486 	padctl->calib.hs_curr_level = level;
1488 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1490 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1501 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1534 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1536 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1538 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1539 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1540 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1541 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1544 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1546 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1548 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1549 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1550 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1551 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1554 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1556 	tegra186_xusb_padctl_save(padctl);
1561 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1563 	tegra186_xusb_padctl_restore(padctl);
1568 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)