phy/tegra/xusb-tegra124.c

220 to_tegra124_xusb_padctl(struct tegra_xusb_padctl *padctl)
222 	return container_of(padctl, struct tegra124_xusb_padctl, base);
225 static int tegra124_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
229 	mutex_lock(&padctl->lock);
231 	if (padctl->enable++ > 0)
234 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
236 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
240 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
242 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
246 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
248 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
251 	mutex_unlock(&padctl->lock);
255 static int tegra124_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
259 	mutex_lock(&padctl->lock);
261 	if (WARN_ON(padctl->enable == 0))
264 	if (--padctl->enable > 0)
267 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
269 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
273 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
275 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
279 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
281 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
284 	mutex_unlock(&padctl->lock);
288 static int tegra124_usb3_save_context(struct tegra_xusb_padctl *padctl,
295 	port = tegra_xusb_find_usb3_port(padctl, index);
302 	if (lane->pad == padctl->pcie)
307 	value = padctl_readl(padctl, offset);
312 	padctl_writel(padctl, value, offset);
314 	value = padctl_readl(padctl, offset) >>
318 	value = padctl_readl(padctl, offset);
323 	padctl_writel(padctl, value, offset);
325 	value = padctl_readl(padctl, offset) >>
329 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
338 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
340 	value = padctl_readl(padctl, offset);
345 	padctl_writel(padctl, value, offset);
347 	value = padctl_readl(padctl, offset);
352 	padctl_writel(padctl, value, offset);
354 	value = padctl_readl(padctl, offset) >>
359 	value = padctl_readl(padctl, offset);
364 	padctl_writel(padctl, value, offset);
366 	value = padctl_readl(padctl, offset) >>
371 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
380 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
385 static int tegra124_hsic_set_idle(struct tegra_xusb_padctl *padctl,
390 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
399 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
468 	return tegra124_xusb_padctl_enable(lane->pad->padctl);
475 	return tegra124_xusb_padctl_disable(lane->pad->padctl);
483 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
490 	port = tegra_xusb_find_usb2_port(padctl, index);
496 	priv = to_tegra124_xusb_padctl(padctl);
498 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
507 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
509 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
514 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
516 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
533 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
535 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
547 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
558 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
560 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
571 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
575 	port = tegra_xusb_find_usb2_port(padctl, lane->index);
590 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
592 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
609 tegra124_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
627 	err = tegra_xusb_pad_init(pad, padctl, np);
717 	return tegra124_xusb_padctl_enable(lane->pad->padctl);
724 	return tegra124_xusb_padctl_disable(lane->pad->padctl);
746 tegra124_ulpi_pad_probe(struct tegra_xusb_padctl *padctl,
762 	err = tegra_xusb_pad_init(pad, padctl, np);
853 	return tegra124_xusb_padctl_enable(lane->pad->padctl);
860 	return tegra124_xusb_padctl_disable(lane->pad->padctl);
868 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
877 	padctl_writel(padctl, hsic->strobe_trim,
880 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
887 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
889 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
906 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
908 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
917 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
919 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
928 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
937 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
941 	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
946 	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
962 tegra124_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
978 	err = tegra_xusb_pad_init(pad, padctl, np);
1073 	return tegra124_xusb_padctl_enable(lane->pad->padctl);
1080 	return tegra124_xusb_padctl_disable(lane->pad->padctl);
1086 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1091 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1093 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1095 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
1099 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
1101 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1103 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1108 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1117 	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1119 	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1127 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1130 	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1132 	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1134 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1136 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
1150 tegra124_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
1166 	err = tegra_xusb_pad_init(pad, padctl, np);
1251 	return tegra124_xusb_padctl_enable(lane->pad->padctl);
1258 	return tegra124_xusb_padctl_disable(lane->pad->padctl);
1264 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1269 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
1272 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
1274 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1277 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1279 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1281 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1283 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1285 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1290 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1299 	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1301 	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1309 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1312 	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1314 	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1316 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1318 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1320 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1322 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1324 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1327 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1329 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
1332 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
1346 tegra124_sata_pad_probe(struct tegra_xusb_padctl *padctl,
1362 	err = tegra_xusb_pad_init(pad, padctl, np);
1421 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1444 	return tegra_xusb_find_lane(port->padctl, "ulpi", port->index);
1466 	return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
1479 	struct tegra_xusb_padctl *padctl = port->padctl;
1484 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1493 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1500 	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
1525 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(index));
1540 	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(index));
1542 	if (lane->pad == padctl->pcie)
1547 	value = padctl_readl(padctl, offset);
1552 	padctl_writel(padctl, value, offset);
1554 	if (lane->pad == padctl->pcie)
1559 	value = padctl_readl(padctl, offset);
1561 	padctl_writel(padctl, value, offset);
1564 	if (lane->pad == padctl->sata) {
1565 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1570 		padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
1572 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL2);
1587 		padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL2);
1589 		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL3);
1591 		padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL3);
1594 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1596 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1600 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1602 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1606 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1608 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1615 	struct tegra_xusb_padctl *padctl = port->padctl;
1618 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1620 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1624 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1626 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1630 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1632 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1634 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1637 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1693 	struct tegra124_xusb_padctl *padctl;
1696 	padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
1697 	if (!padctl)
1700 	padctl->base.dev = dev;
1701 	padctl->base.soc = soc;
1703 	err = tegra124_xusb_read_fuse_calibration(&padctl->fuse);
1707 	return &padctl->base;
1710 static void tegra124_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)