phy/st/phy-stm32-usbphyc.c

138 	struct stm32_usbphyc *usbphyc;
169 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
173 	ret = regulator_enable(usbphyc->vdda1v1);
177 	ret = regulator_enable(usbphyc->vdda1v8);
184 	regulator_disable(usbphyc->vdda1v1);
189 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
193 	ret = regulator_disable(usbphyc->vdda1v8);
197 	ret = regulator_disable(usbphyc->vdda1v1);
231 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
234 	u32 clk_rate = clk_get_rate(usbphyc->clk);
240 		dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
254 	writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
256 	dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
263 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
265 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
272 		dev_err(usbphyc->dev, "PLL not reset\n");
274 	return stm32_usbphyc_regulators_disable(usbphyc);
277 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
280 	if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
283 	return __stm32_usbphyc_pll_disable(usbphyc);
286 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
288 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
296 	if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
304 		dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
306 		ret = __stm32_usbphyc_pll_disable(usbphyc);
311 	ret = stm32_usbphyc_regulators_enable(usbphyc);
315 	ret = stm32_usbphyc_pll_init(usbphyc);
327 	stm32_usbphyc_regulators_disable(usbphyc);
330 	atomic_dec(&usbphyc->n_pll_cons);
338 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
345 	ret = stm32_usbphyc_pll_enable(usbphyc);
350 	writel_relaxed(monsel, usbphyc->base + reg_mon);
351 	ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
355 		dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
365 	stm32_usbphyc_pll_disable(usbphyc);
373 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
377 	return stm32_usbphyc_pll_disable(usbphyc);
410 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
412 	return stm32_usbphyc_pll_enable(usbphyc);
417 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
419 	stm32_usbphyc_pll_disable(usbphyc);
435 	struct stm32_usbphyc *usbphyc = data;
437 	of_clk_del_provider(usbphyc->dev->of_node);
438 	clk_hw_unregister(&usbphyc->clk48_hw);
441 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
443 	struct device_node *node = usbphyc->dev->of_node;
450 	usbphyc->clk48_hw.init = &init;
452 	ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
456 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
458 		clk_hw_unregister(&usbphyc->clk48_hw);
463 static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
466 	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
472 	otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
480 			dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
500 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
515 			dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
523 			dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
531 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
542 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
561 	writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
564 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
568 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
571 		stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
573 	usbphyc->switch_setup = utmi_switch;
579 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
584 	for (port = 0; port < usbphyc->nphys; port++) {
585 		if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
586 			usbphyc_phy = usbphyc->phys[port];
604 		if (usbphyc->switch_setup < 0) {
605 			stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
607 			if (args->args[0] != usbphyc->switch_setup) {
619 	struct stm32_usbphyc *usbphyc;
626 	usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
627 	if (!usbphyc)
629 	usbphyc->dev = dev;
630 	dev_set_drvdata(dev, usbphyc);
632 	usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
633 	if (IS_ERR(usbphyc->base))
634 		return PTR_ERR(usbphyc->base);
636 	usbphyc->clk = devm_clk_get(dev, NULL);
637 	if (IS_ERR(usbphyc->clk))
638 		return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
640 	ret = clk_prepare_enable(usbphyc->clk);
646 	usbphyc->rst = devm_reset_control_get(dev, NULL);
647 	if (!IS_ERR(usbphyc->rst)) {
648 		reset_control_assert(usbphyc->rst);
650 		reset_control_deassert(usbphyc->rst);
652 		ret = PTR_ERR(usbphyc->rst);
656 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
663 	if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
665 		dev_warn(usbphyc->dev, "PLL not reset\n");
670 	usbphyc->switch_setup = -EINVAL;
671 	usbphyc->nphys = of_get_child_count(np);
672 	usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
673 				     sizeof(*usbphyc->phys), GFP_KERNEL);
674 	if (!usbphyc->phys) {
679 	usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
680 	if (IS_ERR(usbphyc->vdda1v1)) {
681 		ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v1),
686 	usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
687 	if (IS_ERR(usbphyc->vdda1v8)) {
688 		ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v8),
715 		if (ret || index > usbphyc->nphys) {
722 		usbphyc->phys[port] = usbphyc_phy;
726 		usbphyc->phys[port]->phy = phy;
727 		usbphyc->phys[port]->usbphyc = usbphyc;
728 		usbphyc->phys[port]->index = index;
729 		usbphyc->phys[port]->active = false;
731 		usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
732 		if (IS_ERR(usbphyc->phys[port]->vbus)) {
733 			ret = PTR_ERR(usbphyc->phys[port]->vbus);
736 			usbphyc->phys[port]->vbus = NULL;
740 		stm32_usbphyc_phy_tuning(usbphyc, child, index);
753 	ret = stm32_usbphyc_clk48_register(usbphyc);
759 	version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
768 	clk_disable_unprepare(usbphyc->clk);
775 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
779 	for (port = 0; port < usbphyc->nphys; port++)
780 		if (usbphyc->phys[port]->active)
781 			stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
783 	stm32_usbphyc_clk48_unregister(usbphyc);
785 	clk_disable_unprepare(usbphyc->clk);
790 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
794 	if (usbphyc->switch_setup >= 0)
795 		stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
797 	for (port = 0; port < usbphyc->nphys; port++) {
798 		usbphyc_phy = usbphyc->phys[port];
799 		writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
808 	{ .compatible = "st,stm32mp1-usbphyc", },
818 		.name = "stm32-usbphyc",