Lines Matching refs:writeb_relaxed
366 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
369 writeb_relaxed(val, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
371 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
376 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset()
379 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset()
390 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); in miphy28lp_pll_calibration()
391 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
394 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
395 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
396 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); in miphy28lp_pll_calibration()
397 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); in miphy28lp_pll_calibration()
398 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); in miphy28lp_pll_calibration()
400 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); in miphy28lp_pll_calibration()
403 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); in miphy28lp_pll_calibration()
410 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); in miphy28lp_pll_calibration()
413 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_pll_calibration()
414 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); in miphy28lp_pll_calibration()
415 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); in miphy28lp_pll_calibration()
416 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); in miphy28lp_pll_calibration()
417 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); in miphy28lp_pll_calibration()
420 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); in miphy28lp_pll_calibration()
434 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_sata_config_gen()
435 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_sata_config_gen()
436 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_sata_config_gen()
437 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_sata_config_gen()
440 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_sata_config_gen()
441 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_sata_config_gen()
444 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_sata_config_gen()
445 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_sata_config_gen()
446 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_sata_config_gen()
447 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_sata_config_gen()
448 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); in miphy28lp_sata_config_gen()
461 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_pcie_config_gen()
462 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_pcie_config_gen()
463 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_pcie_config_gen()
464 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_pcie_config_gen()
467 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); in miphy28lp_pcie_config_gen()
468 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_pcie_config_gen()
469 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_pcie_config_gen()
471 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); in miphy28lp_pcie_config_gen()
474 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_pcie_config_gen()
475 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_pcie_config_gen()
476 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_pcie_config_gen()
477 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_pcie_config_gen()
498 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); in miphy28lp_compensation()
500 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); in miphy28lp_compensation()
501 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_compensation()
502 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); in miphy28lp_compensation()
505 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); in miphy28lp_compensation()
507 writeb_relaxed(0x00, base + MIPHY_RESET); in miphy28lp_compensation()
508 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); in miphy28lp_compensation()
509 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy28lp_compensation()
512 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); in miphy28lp_compensation()
526 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28_usb3_miphy_reset()
527 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28_usb3_miphy_reset()
528 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
531 writeb_relaxed(val, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
533 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); in miphy28_usb3_miphy_reset()
534 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); in miphy28_usb3_miphy_reset()
535 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); in miphy28_usb3_miphy_reset()
536 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
537 writeb_relaxed(0x00, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
538 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); in miphy28_usb3_miphy_reset()
539 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
540 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); in miphy28_usb3_miphy_reset()
541 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); in miphy28_usb3_miphy_reset()
542 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
543 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy28_usb3_miphy_reset()
544 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); in miphy28_usb3_miphy_reset()
545 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
560 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); in miphy_sata_tune_ssc()
564 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy_sata_tune_ssc()
567 writeb_relaxed(val, base + MIPHY_CONF); in miphy_sata_tune_ssc()
571 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy_sata_tune_ssc()
572 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); in miphy_sata_tune_ssc()
573 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); in miphy_sata_tune_ssc()
576 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
579 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
582 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
598 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); in miphy_pcie_tune_ssc()
602 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy_pcie_tune_ssc()
605 writeb_relaxed(val, base + MIPHY_CONF); in miphy_pcie_tune_ssc()
608 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); in miphy_pcie_tune_ssc()
609 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); in miphy_pcie_tune_ssc()
612 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy_pcie_tune_ssc()
613 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); in miphy_pcie_tune_ssc()
616 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
619 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
622 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
629 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); in miphy_tune_tx_impedance()
649 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_sata()
652 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28lp_configure_sata()
664 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
692 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_pcie()
695 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28lp_configure_pcie()
725 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_configure_usb3()
728 writeb_relaxed(val, base + MIPHY_SPEED); in miphy28lp_configure_usb3()
731 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); in miphy28lp_configure_usb3()
732 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); in miphy28lp_configure_usb3()
733 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); in miphy28lp_configure_usb3()
737 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); in miphy28lp_configure_usb3()
738 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); in miphy28lp_configure_usb3()
739 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); in miphy28lp_configure_usb3()
742 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_configure_usb3()
743 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_configure_usb3()
744 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); in miphy28lp_configure_usb3()
747 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); in miphy28lp_configure_usb3()
752 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy28lp_configure_usb3()
755 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); in miphy28lp_configure_usb3()
756 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); in miphy28lp_configure_usb3()
759 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); in miphy28lp_configure_usb3()
762 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_configure_usb3()
765 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); in miphy28lp_configure_usb3()
766 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); in miphy28lp_configure_usb3()
769 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy28lp_configure_usb3()
770 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); in miphy28lp_configure_usb3()
773 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
776 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
779 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
782 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); in miphy28lp_configure_usb3()
786 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_usb3()
787 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_usb3()
788 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); in miphy28lp_configure_usb3()
961 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ in miphy28lp_init_pcie()
962 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ in miphy28lp_init_pcie()
963 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ in miphy28lp_init_pcie()
964 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ in miphy28lp_init_pcie()
965 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ in miphy28lp_init_pcie()
966 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ in miphy28lp_init_pcie()
993 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); in miphy28lp_init_usb3()
994 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); in miphy28lp_init_usb3()
995 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); in miphy28lp_init_usb3()
996 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); in miphy28lp_init_usb3()
997 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); in miphy28lp_init_usb3()
998 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); in miphy28lp_init_usb3()
1001 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); in miphy28lp_init_usb3()
1002 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); in miphy28lp_init_usb3()
1003 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); in miphy28lp_init_usb3()
1004 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); in miphy28lp_init_usb3()
1005 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); in miphy28lp_init_usb3()
1006 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); in miphy28lp_init_usb3()
1007 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); in miphy28lp_init_usb3()
1008 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); in miphy28lp_init_usb3()